Transition maximization techniques for enhancing the two-pattern fault coverage of pseudorandom test pattern generators

Abstract

This paper presents simulation evidence supporting the use of bit transition maximization techniques in the design of hardware test pattern generators (TPGs). Bit transition maximization is a heuristic technique that involves increasing the probability that a bit will change values going from one test pattern to the next. For most of the ISCAS-85 benchmarks and many of the ISCAS-89 benchmarks bit transition maximization enhances the fault coverage of two-pattern faults such as gate delay faults and CMOS transistor stuck-open faults. It achieves these benefits without reducing the fault coverage with respect to classical stuck-at faults.