Performances of a Low Power Latch due to PSN

Abstract

This work describes the working of a low power latch coupled to a typical PDN. The proposed latch is build using a new current steering logic circuit, which draws a constant current from the power supply voltage (Vdd). Simulated in a 90nm CMOS technology and Vdd of 1.1V, the average power and delay are noted to be about 454.4μW and 62.8ps, respectively. Subsequently, a sudden current ramp causes the effective supply voltage close to the die to oscillate. The Ldi/dt is noted to have a minimal effect on the delay.