Taisuke Hayashi, N. Miura, K. Yoshikawa, M. Nagata
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引用次数: 2
Abstract
This paper presents a low-power and compact passive supply-resonance (SR) suppression filter. By using an on-chip waveform monitor, a power-delivery network (PDN) impedance including package, and board PDNs is in-situ analyzed to identify the SR frequency fSR. A notch filter which consists of coupled bonding-wire coils and an on-chip MOS capacitor bank is auto-tuned for the SR suppression. This passive filtering approach reduces the power loss to 1/5~1/10 and the static power to effectively zero as compared to an active SR suppression circuit [1]. The coupled bonding-wire coil enhances its self-inductance and hence shrinks the on-chip capacitor size for the layout-area saving. A 0.18μm CMOS test chip demonstrates SR suppression by >43% with only <;7% of power loss and <;0.034mm layout area penalty.
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