EOS induced transistor shift in submicron DRAMs

Abstract

EOS (Electrical Over-Stress) and ESD (Electro-Static Discharge) damage in sub-micron integrated circuits are often subtle and difficult to characterize. As transistor sizes shrink, we need to be more and more concerned about channel hot electrons (CHC), charge trapping and other "invisible" mechanisms that can degrade device performance. This paper describes an example of just such an occurrence in 0.6 um DRAM where various disciplines were required to successfully isolate the problem. This particular case involved a catastrophic Vt shift at a transistor in the RAS control buffer. Even though this Vt shift was catastrophic from a transistor view-point, the overall electrical performance based on system use conditions was unaffected. This would imply that similar EOS events in system applications could create "walking wounded" devices that may be potential reliability problems.