A 28-GHz, 18-dBm, 48% PAE Stacked-FET Power Amplifier with Coupled-Inductor Neutralization in 45-nm SOI CMOS

Abstract

A single stage, millimeter-wave 2-stack FET power amplifier operates with a peak saturated power of 18.2 dBm and peak PAE of 48.2%. The high PAE results from a proposed $C_{gd}$ neutralization through coupled inductor feedback between the drains of the stacked FETs. The technique reuses the interstage matching shunt inductor to reduce the loss and chip area while improving the PA gain. The PA achieves 13.6 dB gain with a 3 dB bandwidth of 12 GHz at a 2.4-V power supply. The PA is implemented in a 4S-nm SOI CMOS technology using a trap-rich substrate and has an area of $\mathbf{520}\ \mu\mathbf{m}\times \mathbf{530}\ \mu\mathbf{m}$. To the author's knowledge, this work demonstrates the highest gain and power added efficiency (PAE) for a single-stage Si-based PA at 28 GHz.