Technology scaling effects on the ESD design parameters in sub-100 nm CMOS transistors

Abstract

A new phenomenon, reported in this paper for the first time, produces a dramatic reduction of the nMOS and pMOS triggering voltage (V/sub Tl/) under ESD conditions for an ultra-scaled 90 nm CMOS technology used in high performance applications. This V/sub Tl/ reduction is caused by the merging of pocket implants in short gate length transistors. This has a serious impact on the ESD sensitivity of output drivers, placing restrictions on the design of effective protection devices and burn-in voltage during product screening.