Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13/spl mu/m CMOS

Dario Giotta, P. Pessl, M. Clara, Wolfgang Klatzer, R. Gaggl
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引用次数: 33

Abstract

This work presents a 6-bit fully-differential current steering digital-to-analog converter (DAC), oversampled and 2/sup nd/ order noiseshaped. It is implemented in a 0.13 /spl mu/m standard CMOS process, using only regular threshold voltage devices. The circuit is targeted at ADSL2+ central-office (CO) applications. Clocked at 105 MHz from a low-jitter PLL, it yields a multi-tone power ratio (MTPR) higher than 75 dBc for DMT signals, with an output swing of 1.4 V peak-to-peak. It has an effective resolution of more than 14.5 ENOBs (effective number of bits), consuming only 9 mW from a single 1.5 V supply.
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低功耗14位电流转向DAC,适用于0.13/spl mu/m CMOS的ADSL2+/CO应用
这项工作提出了一个6位全差分电流转向数模转换器(DAC),过采样和2/sup /阶噪声整形。它在0.13 /spl mu/m标准CMOS工艺中实现,仅使用常规阈值电压器件。该电路针对ADSL2+中央局(CO)应用。时钟频率为105 MHz,由低抖动锁相环提供,DMT信号的多音功率比(MTPR)高于75 dBc,峰对峰输出摆幅为1.4 V。它具有超过14.5 ENOBs(有效位数)的有效分辨率,单个1.5 V电源仅消耗9 mW。
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