Millimeter-Wave CMOS Phased-Array Transceiver for 5G and Beyond

K. Okada
{"title":"Millimeter-Wave CMOS Phased-Array Transceiver for 5G and Beyond","authors":"K. Okada","doi":"10.1109/IEDM13553.2020.9372045","DOIUrl":null,"url":null,"abstract":"In this presentation, a 28-GHz phased-array transceiver and 300GHz transceiver realized by 65nm CMOS will be introduced, which are designed for 5G and beyond. The talk concludes with a discussion on future directions of millimeter-wave wireless communication, based on Shannon and Friis equations.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM13553.2020.9372045","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

In this presentation, a 28-GHz phased-array transceiver and 300GHz transceiver realized by 65nm CMOS will be introduced, which are designed for 5G and beyond. The talk concludes with a discussion on future directions of millimeter-wave wireless communication, based on Shannon and Friis equations.
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用于5G及以后的毫米波CMOS相控阵收发器
在本次演讲中,将介绍采用65nm CMOS实现的28ghz相控阵收发器和300GHz收发器,这两款收发器专为5G及以后的5G而设计。讲座最后以Shannon和Friis方程为基础,讨论毫米波无线通信的未来发展方向。
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