{"title":"Placement and Routing Methods Based on Mixed Wiring of JTLs and PTLs for RSFQ circuits","authors":"Takashi Dejima, K. Takagi, N. Takagi","doi":"10.1109/ISEC46533.2019.8990903","DOIUrl":null,"url":null,"abstract":"We propose placement and routing methods integrated in automated layout design flow for rapid single-flux-quantum (RSFQ) circuits. In order to realize small circuit area and low latency, both Josephson transmission lines (JTLs) and passive transmission lines (PTLs) are used for interconnects. Placement and routing are performed considering proper use of JTLs and PTLs. The placement problem is divided into subproblems in order to reduce the computational cost. The placement method is composed of three steps, i.e., (i) Cell clustering, (ii) Cell placement and JTL routing in each cluster, and (iii) Cluster placement. Routing among clusters are performed using PTLs. We applied the proposed design flow to sample circuits with several hundreds of gates. Though the circuit area is not fully optimized, the latency of the circuits designed with the proposed methods are smaller than those of the circuits designed manually.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Superconductive Electronics Conference (ISEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISEC46533.2019.8990903","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
We propose placement and routing methods integrated in automated layout design flow for rapid single-flux-quantum (RSFQ) circuits. In order to realize small circuit area and low latency, both Josephson transmission lines (JTLs) and passive transmission lines (PTLs) are used for interconnects. Placement and routing are performed considering proper use of JTLs and PTLs. The placement problem is divided into subproblems in order to reduce the computational cost. The placement method is composed of three steps, i.e., (i) Cell clustering, (ii) Cell placement and JTL routing in each cluster, and (iii) Cluster placement. Routing among clusters are performed using PTLs. We applied the proposed design flow to sample circuits with several hundreds of gates. Though the circuit area is not fully optimized, the latency of the circuits designed with the proposed methods are smaller than those of the circuits designed manually.