Y. Nishi, K. Abe, J. Ribo, B. Roederer, A. Gopalan, M. Benmansour, A. Ho, A. Bhoi, M. Konishi, R. Moriizumi, V. Pathak, S. Gondi
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引用次数: 14
Abstract
A small area PHY transceiver that is compatible with CE16G-LR, CE16G-SR, SAS-6G, PCle and XAUl standards is demonstrated. The 4-channel transceiver is realized in a 90 nm CMOS process with each channel occupying a die area of 0.325 mm2. Power dissipation per channel is less than 230 mW from a 1V supply for 6.25 Gb/s, and scales for data rates down to 1.25 Gb/s.
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