Readability challenges in deeply scaled STT-MRAM

Abstract

Spin transfer torque magnetic random access memory (STT-MRAM) is currently under intensive investigation for one of the possible alternatives to extend the Moore's Law beyond the CMOS technology scaling limit. Its advantageous features, such as nonvolatility, high speed, low power and excellent scalability etc, attract worldwide R&D attention. However as technology scales (e.g., below 40 nm), the process variations introduce big read reliability challenges for STT-MRAM due to the reduced sensing margin (SM) and the increased read disturbance (RD). Therefore the readability, rather than writability, will become an ultimate bottleneck of STT-MRAM at technology nodes below 40 nm. In this paper, we firstly analyze the technology scaling trends on the STT-MRAM read performance; and then we present a RD detection circuit for the case where read current is lower than the write current (e.g., >30 nm); finally we propose a reconfigurable cell design based on the differential sensing scheme to improve the SM and to reduce the RD simultaneously, for the case where read current approaches the write current (e.g., <;30 nm).