Scaling issues in the evolution of ExCL bipolar technology

Abstract

Several issues encountered in scaling ExCL technology are discussed. It is shown that doping profile scaling below 0.15 mu m base width puts severe restrictions on process latitude. It is demonstrated that the polysilicon emitter resistance can be significantly reduced by rapid thermal annealing. Capacitance calculations show that interconnect-related parasitics do not scale below 3 mu m pitch, and intralevel coupling may provide the ultimate limitation of interconnect scaling. Finally, the ExCL metallization scheme is proven to be scalable to 2 mu m metal pitch.<>