Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51081
A.K. Kapoor, H.K. Hingarh, T. S. Jayadev
Operation of poly bipolar npn and p-channel JFET transistors is described up to 10 K. Current gain of the npn transistor equal to 3 is measured at 9 K. Transconductance of the p-channel JFET remains constant for 60 K>T>10 K. Certain new phenomena are observed in both the devices below 60 K which are attributed to carrier freezeout and high-level injection. These experimental results also tend to suggest that the useful range of operation of these devices can be extended to below liquid nitrogen temperature.<>
{"title":"Operation of poly emitter bipolar npn and p-channel JFETs near liquid helium (10 K) temperature","authors":"A.K. Kapoor, H.K. Hingarh, T. S. Jayadev","doi":"10.1109/BIPOL.1988.51081","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51081","url":null,"abstract":"Operation of poly bipolar npn and p-channel JFET transistors is described up to 10 K. Current gain of the npn transistor equal to 3 is measured at 9 K. Transconductance of the p-channel JFET remains constant for 60 K>T>10 K. Certain new phenomena are observed in both the devices below 60 K which are attributed to carrier freezeout and high-level injection. These experimental results also tend to suggest that the useful range of operation of these devices can be extended to below liquid nitrogen temperature.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115748403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51087
J. Siekkinen, G. Neudeck, W. Klaasen
In development of the epitaxial lateral overgrowth (ELO) bipolar transistor, devices were fabricated in silicon selective epitaxial growth (SEG). These devices were used to characterize electrically the quality of the SEG material. Three silicon bipolar transistors with almost identical doping profiles and geometries were simultaneously fabricated on the same wafer and their electrical characteristics compared. The three transistors were located in the substrate, a single SEG layer, and a double (interrupted growth) SEG layer. The SEG silicon was grown in a reduced pressure, RF-heated, pancake-type epitaxial reactor at 950 degrees C and 150 torr. The transistors were tested for junction ideality factors, junction reverse bias leakage currents, and forward DC current gain. Test results showed average ideality factors, leakage currents, and gains were similar for all device types, indicating the excellent device quality of the SEG material relative to the substrate.<>
{"title":"SEG/ELO material characterization using silicon bipolar transistors","authors":"J. Siekkinen, G. Neudeck, W. Klaasen","doi":"10.1109/BIPOL.1988.51087","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51087","url":null,"abstract":"In development of the epitaxial lateral overgrowth (ELO) bipolar transistor, devices were fabricated in silicon selective epitaxial growth (SEG). These devices were used to characterize electrically the quality of the SEG material. Three silicon bipolar transistors with almost identical doping profiles and geometries were simultaneously fabricated on the same wafer and their electrical characteristics compared. The three transistors were located in the substrate, a single SEG layer, and a double (interrupted growth) SEG layer. The SEG silicon was grown in a reduced pressure, RF-heated, pancake-type epitaxial reactor at 950 degrees C and 150 torr. The transistors were tested for junction ideality factors, junction reverse bias leakage currents, and forward DC current gain. Test results showed average ideality factors, leakage currents, and gains were similar for all device types, indicating the excellent device quality of the SEG material relative to the substrate.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124835234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51077
S. Jain, R. Mertens, P. van Mieghem, M. Mauk, M. Ghannam, G. Borghs, R. van Overstraeten
The effect of heavy doping on the capacitance-voltage relation of abrupt and linearly-graded p-n junctions is studied by computer simulations. An estimate of bandgap narrowing in compensated silicon is given for linearly-graded junctions. Capacitance-voltage curves of abrupt p-n GaAs junctions grown by MBE are investigated and compared to the theoretical curves.<>
{"title":"Effects of bandgap narrowing on the capacitance of silicon and GaAs pn junctions","authors":"S. Jain, R. Mertens, P. van Mieghem, M. Mauk, M. Ghannam, G. Borghs, R. van Overstraeten","doi":"10.1109/BIPOL.1988.51077","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51077","url":null,"abstract":"The effect of heavy doping on the capacitance-voltage relation of abrupt and linearly-graded p-n junctions is studied by computer simulations. An estimate of bandgap narrowing in compensated silicon is given for linearly-graded junctions. Capacitance-voltage curves of abrupt p-n GaAs junctions grown by MBE are investigated and compared to the theoretical curves.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131366090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51072
W. John
Macromodels for the description of ALS-gate behavior have been developed. It is shown that such models describe the static and dynamic input and output behavior of a gate completely. A main advantage of the introduced macromodel structure is the low number of network nodes. The example presented here shows the good coincidence of the macromodel with the reference values obtained by simulation of the whole gate. An extensive development is planned in the area of model building for tolerance behavior of gates with respect to V/sub cc/ and temperature influence. An application of the presented macromodel structure is planned for HCMOS and ACL technologies.<>
{"title":"Development of macromodels for description of ALS-gate-behaviour with respect to high-speed applications","authors":"W. John","doi":"10.1109/BIPOL.1988.51072","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51072","url":null,"abstract":"Macromodels for the description of ALS-gate behavior have been developed. It is shown that such models describe the static and dynamic input and output behavior of a gate completely. A main advantage of the introduced macromodel structure is the low number of network nodes. The example presented here shows the good coincidence of the macromodel with the reference values obtained by simulation of the whole gate. An extensive development is planned in the area of model building for tolerance behavior of gates with respect to V/sub cc/ and temperature influence. An application of the presented macromodel structure is planned for HCMOS and ACL technologies.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130092263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51054
D. Burnett, C. Hu
The degradation of self-aligned, polysilicon emitter transistors is described for a wide range of constant current stress on several device sizes. The experimental results indicate that Delta I/sub B/ can be expressed as AQ/sup n/, with n=0.5 for these devices. Except for large values of I/sub R/, A varies in a power-lay fashion with I/sub R/. The dependence of Delta I/sub B/ upon the forward current at which the device is operating can be expressed as A=BJ/sup gamma //sub C/. It is observed that n is characteristic of all devices and stress currents, B is constant for a given device size, and gamma varies with device size and reverse current.<>
{"title":"Hot-carrier effects in polysilicon emitter bipolar transistors","authors":"D. Burnett, C. Hu","doi":"10.1109/BIPOL.1988.51054","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51054","url":null,"abstract":"The degradation of self-aligned, polysilicon emitter transistors is described for a wide range of constant current stress on several device sizes. The experimental results indicate that Delta I/sub B/ can be expressed as AQ/sup n/, with n=0.5 for these devices. Except for large values of I/sub R/, A varies in a power-lay fashion with I/sub R/. The dependence of Delta I/sub B/ upon the forward current at which the device is operating can be expressed as A=BJ/sup gamma //sub C/. It is observed that n is characteristic of all devices and stress currents, B is constant for a given device size, and gamma varies with device size and reverse current.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133837771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51058
M. Jo, D. Burk
A multiregional small-signal model is derived from a charge-based large-signal bipolar transistor model, which has been upgraded to include emitter crowding, sidewall injection, and other multidimensional effects. This multiregional model is verified and the effect of this three-region analysis of the parameter extraction for the small-signal transistor model over a range of (low to high) injection conditions is demonstrated.<>
{"title":"A multi-regional small-signal model derived from the charge-based large-signal bipolar transistor model","authors":"M. Jo, D. Burk","doi":"10.1109/BIPOL.1988.51058","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51058","url":null,"abstract":"A multiregional small-signal model is derived from a charge-based large-signal bipolar transistor model, which has been upgraded to include emitter crowding, sidewall injection, and other multidimensional effects. This multiregional model is verified and the effect of this three-region analysis of the parameter extraction for the small-signal transistor model over a range of (low to high) injection conditions is demonstrated.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124440388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51064
B. van Schravendijk, J. de Jong, J. de Groot, P. Maillot
The method of double-diffused emitter-base formation is characterized. It is shown to be a viable technique for the fabrication of advanced bipolar transistors. The use of amorphous instead of polycrystalline silicon as the emitter contact material results in a shallower emitter-base junction and little effect of the boron diffusion on the obtained arsenic profile. The narrowing of the base yields a higher intrinsic base resistance for the same number of carriers leading to a decrease in current gain for the same intrinsic base resistance. The different processing of double diffusion compared to base implantation may also lead to a loss in emitter efficiency. Nevertheless uniformity of the basewidth seems to be excellent and good high-frequency characteristics (up to f/sub T/=15 GHz) are obtained.<>
{"title":"Thin base formation by double diffused polysilicon technology","authors":"B. van Schravendijk, J. de Jong, J. de Groot, P. Maillot","doi":"10.1109/BIPOL.1988.51064","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51064","url":null,"abstract":"The method of double-diffused emitter-base formation is characterized. It is shown to be a viable technique for the fabrication of advanced bipolar transistors. The use of amorphous instead of polycrystalline silicon as the emitter contact material results in a shallower emitter-base junction and little effect of the boron diffusion on the obtained arsenic profile. The narrowing of the base yields a higher intrinsic base resistance for the same number of carriers leading to a decrease in current gain for the same intrinsic base resistance. The different processing of double diffusion compared to base implantation may also lead to a loss in emitter efficiency. Nevertheless uniformity of the basewidth seems to be excellent and good high-frequency characteristics (up to f/sub T/=15 GHz) are obtained.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114668635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51060
B. Landau, B. Bastani, D. Haueisen, R. Lahri, S. P. Joshi, J. Small
Two approaches involving phosphorus- and arsenic-doped poly emitters for bipolar device optimization in a 1 mu m BiCMOS process are reported. An evaluation includes a comparison of process and device parameters for the two emitter types in the context of a junction-isolated process. The impact of device optimization as measured by ECL and BiCMOS ring oscillators and a BiCMOS 256 K SRAM is discussed. Finally, the reliability of phosphorus and arsenic poly emitters, in terms of beta degradation due to reverse biasing of the emitter-base junction, is presented.<>
本文报道了在1 μ m BiCMOS工艺中采用磷和砷掺杂多发射体对双极器件进行优化的两种方法。评估包括在连接隔离工艺的背景下对两种发射器类型的工艺和器件参数进行比较。讨论了ECL和BiCMOS环形振荡器以及BiCMOS 256k SRAM测量的器件优化的影响。最后，磷和砷多发射体的可靠性，在β降解方面，由于反向偏置的发射极-基结，提出
{"title":"Poly emitter bipolar transistor optimization for an advanced BiCMOS technology","authors":"B. Landau, B. Bastani, D. Haueisen, R. Lahri, S. P. Joshi, J. Small","doi":"10.1109/BIPOL.1988.51060","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51060","url":null,"abstract":"Two approaches involving phosphorus- and arsenic-doped poly emitters for bipolar device optimization in a 1 mu m BiCMOS process are reported. An evaluation includes a comparison of process and device parameters for the two emitter types in the context of a junction-isolated process. The impact of device optimization as measured by ECL and BiCMOS ring oscillators and a BiCMOS 256 K SRAM is discussed. Finally, the reliability of phosphorus and arsenic poly emitters, in terms of beta degradation due to reverse biasing of the emitter-base junction, is presented.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132326441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51044
G. Wolstenholme, P. Ashburn, N. Jorgensen, D. Gold, G. Booker
A method for measuring the emitter resistance of polysilicon emitter transistors is described that separates the interface and metal/polysilicon contact components of the emitter resistance. Results show that for devices with a continuous interfacial layer the interface resistance controls the emitter resistance and is between 200 and 450 Omega mu m/sup 2/. This resistance is found to be current dependent and good agreement between theory and experiment is obtained. Results for devices with a discontinuous interfacial layer indicate that low interface resistances (17-33 Omega mu m/sup 2/) suitable for VLSI applications can be obtained by deliberately breaking up the interfacial layer. In this case the metal contact resistance contributes significantly to the total emitter resistance.<>
{"title":"Measurement and modelling of the emitter resistance of polysilicon emitter transistors","authors":"G. Wolstenholme, P. Ashburn, N. Jorgensen, D. Gold, G. Booker","doi":"10.1109/BIPOL.1988.51044","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51044","url":null,"abstract":"A method for measuring the emitter resistance of polysilicon emitter transistors is described that separates the interface and metal/polysilicon contact components of the emitter resistance. Results show that for devices with a continuous interfacial layer the interface resistance controls the emitter resistance and is between 200 and 450 Omega mu m/sup 2/. This resistance is found to be current dependent and good agreement between theory and experiment is obtained. Results for devices with a discontinuous interfacial layer indicate that low interface resistances (17-33 Omega mu m/sup 2/) suitable for VLSI applications can be obtained by deliberately breaking up the interfacial layer. In this case the metal contact resistance contributes significantly to the total emitter resistance.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122265990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/BIPOL.1988.51034
H. Ichino, M. Suzuki, S. Konaka, T. Wakimoto, T. Sakai
SST-1B technology, an advanced version of SST-1A, and its applications are described. The main feature is utilization of the selectively ion-implanted collector process to improve shallow base-collector profiles to reduce base width and intrinsic base resistance, and to suppress the base pushout effect. A cutoff frequency of 25.7 GHz and the basic gate delays of 20.5 ps for NTL and 34.1 ps for ECL have been obtained. Using this technology, a number of very high-speed ICs-a 18-GHz 1/8 divider, a 2-Gbsps 6-bit AD converter, and 43-ps/5.2-GHz macrocell array LSIs-have been developed. Concerning future performance, a cutoff frequency of more than 50 GHz for a scaled-down transistor is expected.<>
{"title":"Super self-aligned process technology (SST) and its applications","authors":"H. Ichino, M. Suzuki, S. Konaka, T. Wakimoto, T. Sakai","doi":"10.1109/BIPOL.1988.51034","DOIUrl":"https://doi.org/10.1109/BIPOL.1988.51034","url":null,"abstract":"SST-1B technology, an advanced version of SST-1A, and its applications are described. The main feature is utilization of the selectively ion-implanted collector process to improve shallow base-collector profiles to reduce base width and intrinsic base resistance, and to suppress the base pushout effect. A cutoff frequency of 25.7 GHz and the basic gate delays of 20.5 ps for NTL and 34.1 ps for ECL have been obtained. Using this technology, a number of very high-speed ICs-a 18-GHz 1/8 divider, a 2-Gbsps 6-bit AD converter, and 43-ps/5.2-GHz macrocell array LSIs-have been developed. Concerning future performance, a cutoff frequency of more than 50 GHz for a scaled-down transistor is expected.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121251420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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