Invited talk: Computing beyond the 11nm node: Which devices will we use?

Abstract

Summary form only given. The enormous success of Si CMOS technology is based on the economy of scale. Cost is driven down by increasing wafer size and decreasing feature sizes while performance is steadily growing. The pervasive nature of microelectronic can be seen in all aspects of daily life. The industry enjoyed the success story for several decades by simply following the scaling laws. More recently it is realized that increased performance will come at an unacceptable cost of power and conventional CMOS scaling is rapidly coming to an end. The quest for solutions is in full swing how to meet the computational demands for the foreseeable future. Possible solutions are the change of device architecture and the introduction of high mobility materials for the devices to boost performance. Beyond the classical device materials Si, Ge, and some III/V compounds carbon in the form of carbon nano tubes or graphene are suggested as possible alternative candidates for digital applications. Replacing the field effect transistor by a tunnel FET holds the promise of a low power switch that can be realized with conventional channel materials. Moving from electrical charge to other state variables, like for instance spin, might provide new possibilities to meet the computational needs in the future.