Invited tutorial: Channel equalization: Techniques for high-speed electrical links

Abstract

Summary form only given. While high-performance I/O circuitry can leverage the technology improvements that enable increased on-chip performance, unfortunately the bandwidth of the electrical channels used for inter-chip communication has not scaled in the same manner. This tutorial provides an overview of channel equalization techniques used in multi-Gb/s transceivers to overcome bandwidth limitations present in electrical chip-to-chip communication. The first part of the tutorial will cover the dominant sources of electrical interconnect channel losses, such as skin effect, dielectric loss, and reflections due to impedance discontinuities. Next, trade-offs and circuit implementations of common equalizer circuits, including finite-impulse-response (FIR) filters, continuous-time linear equalizers (CTLE), and decision-feedback equalizers (DFE), are detailed. The performance impact of these different equalizer topologies over real-world channels is illustrated using a statistical link analysis tool and through a comparison of several recent high-performance I/O transceiver implementations. Finally, the tutorial concludes with a discussion on different equalizer adaptation techniques.