Pub Date : 2013-04-12DOI: 10.1109/WMED.2013.6544496
S. Groothuis
The goal of the course is to give you a brief overview of MEMS technologies by covering packaging, reliability, simulation, and testing. We will venture into recent developments like Sensor Fusion, Integrated CMOS-MEMS, and BioMEMS. You will gain an in-depth knowledge of challenges and opportunities associated with bringing MEMS-based products to market through the course's focus on two key topics: (1) MEMS Packaging - You will learn packaging concepts for MEMS devices while reviewing assembly and packaging procedures such as structural release, cleaning, encapsulation, and testing. The tutorial will also cover various challenges associated with packaging and testing MEMS. (2) MEMS Reliability - This tutorial will review MEMS reliability issues and associated analysis/simulation techniques. MEMS reliability requires a broad understanding of physics, material science, and mechanics in order to handle the challenges during research, development, and productization.
{"title":"Invited tutorial: MEMS: Driving advances in electronic devices","authors":"S. Groothuis","doi":"10.1109/WMED.2013.6544496","DOIUrl":"https://doi.org/10.1109/WMED.2013.6544496","url":null,"abstract":"The goal of the course is to give you a brief overview of MEMS technologies by covering packaging, reliability, simulation, and testing. We will venture into recent developments like Sensor Fusion, Integrated CMOS-MEMS, and BioMEMS. You will gain an in-depth knowledge of challenges and opportunities associated with bringing MEMS-based products to market through the course's focus on two key topics: (1) MEMS Packaging - You will learn packaging concepts for MEMS devices while reviewing assembly and packaging procedures such as structural release, cleaning, encapsulation, and testing. The tutorial will also cover various challenges associated with packaging and testing MEMS. (2) MEMS Reliability - This tutorial will review MEMS reliability issues and associated analysis/simulation techniques. MEMS reliability requires a broad understanding of physics, material science, and mechanics in order to handle the challenges during research, development, and productization.","PeriodicalId":134493,"journal":{"name":"2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125093356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-12DOI: 10.1109/WMED.2013.6544510
D. Elgamel, L. Barannyk, A. Elshabini, F. Barlow
Passivity enforcement techniques are widely used in DRAM package model development. The Hamiltonian method is one of the common methods used for checking/enforcing passivity of these multiport networks. Enforcing the passivity for non-passive models is not trivial because it is built on several approximation steps starting from building the macromodel, which captures the frequency domain response, and ending with a suitable spice model for the DRAM circuits. Several approximation steps take place to achieve that result, and multiple constraints are used to preserve the original design characteristics. In this paper, we compared residue perturbation with and without error control in order to calculate how passivity enforcement affects the original model accuracy.
{"title":"Comparison of passive enforcement techniques for DRAM package models","authors":"D. Elgamel, L. Barannyk, A. Elshabini, F. Barlow","doi":"10.1109/WMED.2013.6544510","DOIUrl":"https://doi.org/10.1109/WMED.2013.6544510","url":null,"abstract":"Passivity enforcement techniques are widely used in DRAM package model development. The Hamiltonian method is one of the common methods used for checking/enforcing passivity of these multiport networks. Enforcing the passivity for non-passive models is not trivial because it is built on several approximation steps starting from building the macromodel, which captures the frequency domain response, and ending with a suitable spice model for the DRAM circuits. Several approximation steps take place to achieve that result, and multiple constraints are used to preserve the original design characteristics. In this paper, we compared residue perturbation with and without error control in order to calculate how passivity enforcement affects the original model accuracy.","PeriodicalId":134493,"journal":{"name":"2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"9 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114097033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-12DOI: 10.1109/WMED.2013.6544508
Kehan Zhu, S. Balagopal, V. Saxena
A systematical design analysis of a 10-bit 50MS/s pipelined ADC is presented. With an opamp-sharing technique, the power consumption is reduced drastically. Simulated in a 130-nm CMOS process, it achieves a 58.9dB signal-to-noise ratio (SNR), a 9.3 effective number of bits (ENOB), 64dB spurious free dynamic range (SFDR) with a sinusoid input of 4.858-MHz 1-Vpp at 50MS/s, and consumes less than 24 mW from a 1.2-V supply.
{"title":"Systematic design of 10-bit 50MS/s pipelined ADC","authors":"Kehan Zhu, S. Balagopal, V. Saxena","doi":"10.1109/WMED.2013.6544508","DOIUrl":"https://doi.org/10.1109/WMED.2013.6544508","url":null,"abstract":"A systematical design analysis of a 10-bit 50MS/s pipelined ADC is presented. With an opamp-sharing technique, the power consumption is reduced drastically. Simulated in a 130-nm CMOS process, it achieves a 58.9dB signal-to-noise ratio (SNR), a 9.3 effective number of bits (ENOB), 64dB spurious free dynamic range (SFDR) with a sinusoid input of 4.858-MHz 1-Vpp at 50MS/s, and consumes less than 24 mW from a 1.2-V supply.","PeriodicalId":134493,"journal":{"name":"2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126080502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-12DOI: 10.1109/WMED.2013.6544499
R. Murphy
Summary form only given. The memory system is typically the primary driver behind system performance, which has been acknowledged as the von Neumann bottleneck since the invention of the modern electronic computer in the 1940s. Tremendous unsustainable investments have been made on the processor side to attempt to get around the problem. However, the end of Dennard Scaling in 2003 meant that the memory wall must finally be addressed to support the transition to simpler, multicore architectures. Consequently, computer architects must consider the fundamental system-level tradeoffs, rather than myopically focusing on CPU core architecture. This talk will describe the first decade of the transition into the new era of computer architecture, its impact on application performance, and what we as a community can do about it.
{"title":"Invited talk: Memory: The center of the universe","authors":"R. Murphy","doi":"10.1109/WMED.2013.6544499","DOIUrl":"https://doi.org/10.1109/WMED.2013.6544499","url":null,"abstract":"Summary form only given. The memory system is typically the primary driver behind system performance, which has been acknowledged as the von Neumann bottleneck since the invention of the modern electronic computer in the 1940s. Tremendous unsustainable investments have been made on the processor side to attempt to get around the problem. However, the end of Dennard Scaling in 2003 meant that the memory wall must finally be addressed to support the transition to simpler, multicore architectures. Consequently, computer architects must consider the fundamental system-level tradeoffs, rather than myopically focusing on CPU core architecture. This talk will describe the first decade of the transition into the new era of computer architecture, its impact on application performance, and what we as a community can do about it.","PeriodicalId":134493,"journal":{"name":"2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127801161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-12DOI: 10.1109/WMED.2013.6544494
C. Mack
Summary form only given. Moore's Law is the defining feature of the information age. First expressed by Gordon Moore in 1965, Moore's Law says that the number of transistors on an integrated circuit doubles every one to two years. The result over the last fifty years has been dramatic improvements in computational capabilities, communications, entertainment, and all aspects of electronic technology, all at ever lower cost. Quite literally, Moore's Law has brought about a radical change in society, with implications for human civilization that are not fully resolved. But Moore's Law itself has undergone changes over the last 50 years. There have been three phases of Moore's Law, with the latest phase, what I call Moore's Law 3.0, recently becoming dominant. This talk will describe the history of Moore's Law, and the technical and economic forces that have shaped it. Tennant's Law, which relates cost to resolution, and the role of wafer size (and in particular the planned move to 450-mm diameter wafers) will also be discussed. The three Moore's Law eras will be explained, and the implications of the current Moore's Law 3.0 era on the future of technology development will be discussed. Warning: some speculations will be inevitable.
{"title":"Keynote: Moore's Law 3.0","authors":"C. Mack","doi":"10.1109/WMED.2013.6544494","DOIUrl":"https://doi.org/10.1109/WMED.2013.6544494","url":null,"abstract":"Summary form only given. Moore's Law is the defining feature of the information age. First expressed by Gordon Moore in 1965, Moore's Law says that the number of transistors on an integrated circuit doubles every one to two years. The result over the last fifty years has been dramatic improvements in computational capabilities, communications, entertainment, and all aspects of electronic technology, all at ever lower cost. Quite literally, Moore's Law has brought about a radical change in society, with implications for human civilization that are not fully resolved. But Moore's Law itself has undergone changes over the last 50 years. There have been three phases of Moore's Law, with the latest phase, what I call Moore's Law 3.0, recently becoming dominant. This talk will describe the history of Moore's Law, and the technical and economic forces that have shaped it. Tennant's Law, which relates cost to resolution, and the role of wafer size (and in particular the planned move to 450-mm diameter wafers) will also be discussed. The three Moore's Law eras will be explained, and the implications of the current Moore's Law 3.0 era on the future of technology development will be discussed. Warning: some speculations will be inevitable.","PeriodicalId":134493,"journal":{"name":"2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124747565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-12DOI: 10.1109/WMED.2013.6544506
A. Abdelnaby, G. Potirniche, F. Barlow, A. Elshabini, S. Groothuis, R. Parker
Wafer warpage is one of the most important challenges in the fabrication of modern electronic devices. Other challenges include handling, tool faults, and misalignments and even wafer breakage. The wafer warpage translates into die warpage that has a remarkable impact on die pick, stack and attach. This paper describes the work performed to simulate the silicon wafer warpage as a function of the wafer thickness and the film stresses using the commercial finite element code ABAQUS. The model accounts for the silicon anisotropy to better simulate the deformation. The computed values of the warpage were compared with experimental data and showed good correlation. The numerical model developed can be used to better understand the relation between the film stress and the wafer warpage. Furthermore it can be used to predict the warpage based on the wafer thickness and the film stress, which can help mitigate the warpage by depositing films to reduce the overall wafer warpage.
{"title":"Numerical simulation of silicon wafer warpage due to thin film residual stresses","authors":"A. Abdelnaby, G. Potirniche, F. Barlow, A. Elshabini, S. Groothuis, R. Parker","doi":"10.1109/WMED.2013.6544506","DOIUrl":"https://doi.org/10.1109/WMED.2013.6544506","url":null,"abstract":"Wafer warpage is one of the most important challenges in the fabrication of modern electronic devices. Other challenges include handling, tool faults, and misalignments and even wafer breakage. The wafer warpage translates into die warpage that has a remarkable impact on die pick, stack and attach. This paper describes the work performed to simulate the silicon wafer warpage as a function of the wafer thickness and the film stresses using the commercial finite element code ABAQUS. The model accounts for the silicon anisotropy to better simulate the deformation. The computed values of the warpage were compared with experimental data and showed good correlation. The numerical model developed can be used to better understand the relation between the film stress and the wafer warpage. Furthermore it can be used to predict the warpage based on the wafer thickness and the film stress, which can help mitigate the warpage by depositing films to reduce the overall wafer warpage.","PeriodicalId":134493,"journal":{"name":"2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134527318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-12DOI: 10.1109/WMED.2013.6544497
S. Palermo
Summary form only given. While high-performance I/O circuitry can leverage the technology improvements that enable increased on-chip performance, unfortunately the bandwidth of the electrical channels used for inter-chip communication has not scaled in the same manner. This tutorial provides an overview of channel equalization techniques used in multi-Gb/s transceivers to overcome bandwidth limitations present in electrical chip-to-chip communication. The first part of the tutorial will cover the dominant sources of electrical interconnect channel losses, such as skin effect, dielectric loss, and reflections due to impedance discontinuities. Next, trade-offs and circuit implementations of common equalizer circuits, including finite-impulse-response (FIR) filters, continuous-time linear equalizers (CTLE), and decision-feedback equalizers (DFE), are detailed. The performance impact of these different equalizer topologies over real-world channels is illustrated using a statistical link analysis tool and through a comparison of several recent high-performance I/O transceiver implementations. Finally, the tutorial concludes with a discussion on different equalizer adaptation techniques.
{"title":"Invited tutorial: Channel equalization: Techniques for high-speed electrical links","authors":"S. Palermo","doi":"10.1109/WMED.2013.6544497","DOIUrl":"https://doi.org/10.1109/WMED.2013.6544497","url":null,"abstract":"Summary form only given. While high-performance I/O circuitry can leverage the technology improvements that enable increased on-chip performance, unfortunately the bandwidth of the electrical channels used for inter-chip communication has not scaled in the same manner. This tutorial provides an overview of channel equalization techniques used in multi-Gb/s transceivers to overcome bandwidth limitations present in electrical chip-to-chip communication. The first part of the tutorial will cover the dominant sources of electrical interconnect channel losses, such as skin effect, dielectric loss, and reflections due to impedance discontinuities. Next, trade-offs and circuit implementations of common equalizer circuits, including finite-impulse-response (FIR) filters, continuous-time linear equalizers (CTLE), and decision-feedback equalizers (DFE), are detailed. The performance impact of these different equalizer topologies over real-world channels is illustrated using a statistical link analysis tool and through a comparison of several recent high-performance I/O transceiver implementations. Finally, the tutorial concludes with a discussion on different equalizer adaptation techniques.","PeriodicalId":134493,"journal":{"name":"2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123943048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-12DOI: 10.1109/WMED.2013.6544498
W. Lu
Summary form only given. Nanoscale resistive memories (RRAMs) have generated extensive interest recently as a promising candidate for future non-volatile memory applications. In this talk, I will briefly summarize the current status of RRAM research, from the switching mechanism, modeling, material choice, performance metrics, to prototype memory demonstrations. Recently improved understanding of the resistance switching effects has led to improved device performance. However, challenges such as the tradeoff between programming current and retention still need to be overcome. Another major challenge for RRAM is the “sneak path” problem in the interconnected passive network, and proper “select” elements need to be developed to break the parasitic paths. Effective 3D integration techniques also need to be demonstrated. Different approaches to address these problems will be discussed.
{"title":"Invited talk: Resistive random access memory (RRAM): Materials and devices","authors":"W. Lu","doi":"10.1109/WMED.2013.6544498","DOIUrl":"https://doi.org/10.1109/WMED.2013.6544498","url":null,"abstract":"Summary form only given. Nanoscale resistive memories (RRAMs) have generated extensive interest recently as a promising candidate for future non-volatile memory applications. In this talk, I will briefly summarize the current status of RRAM research, from the switching mechanism, modeling, material choice, performance metrics, to prototype memory demonstrations. Recently improved understanding of the resistance switching effects has led to improved device performance. However, challenges such as the tradeoff between programming current and retention still need to be overcome. Another major challenge for RRAM is the “sneak path” problem in the interconnected passive network, and proper “select” elements need to be developed to break the parasitic paths. Effective 3D integration techniques also need to be demonstrated. Different approaches to address these problems will be discussed.","PeriodicalId":134493,"journal":{"name":"2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"57 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128007762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-12DOI: 10.1109/WMED.2013.6544509
H. Aboutaleb, L. L. Baranny, A. Elshabini, F. Barlow
Causality verification and enforcement is an essential step in generating high speed electric package macromodels and it often accomplished in two steps: vector fitting measured system parameters into a rational function representation and then performing the Hilbert Transform integrations to check and if needed enforce causality. This procedure suffers from various approximation, truncation, and discretization errors. Besides, the measured or simulated system data are known only on the finite bandwidth, while the Hilbert Transform has to be computed on the infinite domain. To avoid these errors as well as inaccuracy of extrapolation of the transfer function to infinity, a new method is proposed to check and enforce causality by using raw bandlimited data that is extended periodically using a polynomial interpolation and computing the Hilbert Transform of the periodically extended data via accurate FFT.
{"title":"A new method for causality enforcement of DRAM package models using discrete hilbert transforms","authors":"H. Aboutaleb, L. L. Baranny, A. Elshabini, F. Barlow","doi":"10.1109/WMED.2013.6544509","DOIUrl":"https://doi.org/10.1109/WMED.2013.6544509","url":null,"abstract":"Causality verification and enforcement is an essential step in generating high speed electric package macromodels and it often accomplished in two steps: vector fitting measured system parameters into a rational function representation and then performing the Hilbert Transform integrations to check and if needed enforce causality. This procedure suffers from various approximation, truncation, and discretization errors. Besides, the measured or simulated system data are known only on the finite bandwidth, while the Hilbert Transform has to be computed on the infinite domain. To avoid these errors as well as inaccuracy of extrapolation of the transfer function to infinity, a new method is proposed to check and enforce causality by using raw bandlimited data that is extended periodically using a polynomial interpolation and computing the Hilbert Transform of the periodically extended data via accurate FFT.","PeriodicalId":134493,"journal":{"name":"2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"116 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117222551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-12DOI: 10.1109/WMED.2013.6544507
D. Sullivan
A three-dimensional simulation using the finite-difference time-domain (FDTD) method is being used to determine transmission through FinFETs. A waveform representing a particle is analyzed before and after it goes through the channel using a three-dimensional spatial sine transform to produce functions of energy. The ratio of these two functions is used to calculate transmission. From the transmission, the quantum conductance of the channel can be calculated.
{"title":"Three-dimensional FinFET simulation using the FDTD method","authors":"D. Sullivan","doi":"10.1109/WMED.2013.6544507","DOIUrl":"https://doi.org/10.1109/WMED.2013.6544507","url":null,"abstract":"A three-dimensional simulation using the finite-difference time-domain (FDTD) method is being used to determine transmission through FinFETs. A waveform representing a particle is analyzed before and after it goes through the channel using a three-dimensional spatial sine transform to produce functions of energy. The ratio of these two functions is used to calculate transmission. From the transmission, the quantum conductance of the channel can be calculated.","PeriodicalId":134493,"journal":{"name":"2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125006821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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