Ultra-low thermal budget CMOS process for 65nm-node low-operation-power applications

Abstract

This paper describes the fabrication process and the performance of 65 nm-node CMOS transistors which have ultra-shallow junctions. Flash lamp annealing enhances the drivability of pFETs with a solid phase epitaxial extension junction. The increase in the junction leakage of the extension junction is less than 1 order of magnitude as compared with that for the conventional spike RTA on a 300 mm/spl phi/ wafer. Excellent Vth control at 35 nm gate length without halo implantation and a high switching speed at 0.9 V power supply are demonstrated for 65 nm-node LOP (low operation power) applications.