Defect Aware to Power Conscious Tests - The New DFT Landscape

Abstract

The rapid scaling of semiconductor devices along with technological innovations including material and process changes such as high-k gate dielectric, metal gate electrodes, etc., are making conventional fault models inadequate. In addition, the evolution of interconnects from single to multiple-levels, the use of new materials to meet the wire conductivity requirements and reduce dielectric permittivity, and the scaling of conventional metal/dielectric system have had significant impact on the performance and power dissipation of devices. Multi-core designs, heterogeneous component integration, and sophisticated packaging techniques further aggravate the challenge of testing such devices effectively. This tutorial will focus on some of the advances shaping the test industry today to address the above mentioned design and process changes. New fault models that are termed as “defect aware” are being proposed and there is a demand for test vectors targeting such defects. Bridging (static and dynamic), n-detect, stuck-open, inlineresistance, propagation delay, etc., are some examples of new fault models that are being used to various extent in the industry today. At the same time, at-speed testing is becoming the norm as the industry moves towards smaller technology nodes. Methods to handle false and multi-cycle paths effectively are common in practice to prevent unnecessary yield losses. For the first time, timing information is being considered during Automatic Test Pattern Generation (ATPG) targeting small-delay defects. Each one of the fault models will be discussed and the current trends in the industry along with some preliminary silicon experiments will be presented. Another industry trend posing a serious challenge to manufacturing test is the advent of poweraware designs. Various techniques such as architecture driven voltage reduction, switching activity minimization, switched capacitance minimization, and dynamic power management are being deployed in designing low power devices. New DFT techniques are required as well to limit power dissipation during test (preferably matching the power dissipation in functional mode of operation) thereby preventing IR drops, voltage droop, or hot spots. Test pattern generation needs to be tweaked to consider power dissipation during the key steps of the algorithm. In this tutorial, methods to control power dissipation during test, both from DFT as well as test generation perspectives will be discussed. As numerous fault models are being proposed, all the different pattern sets along with poweraware test pattern generation results in a significant increase in the number of patterns. This directly impacts test cost as both test application time as well as the tester memory needed to store the vectors are increasing. Compression schemes with not only aggressive compression ratios are being adopted; they need to fit into the low power DFT methodology. This tutorial will highlight some methods to handle low power designs with compression. Additionally, advanced compression schemes to handle very large compression ratios will be discussed.