Verification and test of real circuits

Abstract

For the verification and functional safety of real systems, e.g. of analog and digital circuits, the function associated with the real structure must be modelled with structural integrity ensured. This means that the consistency of the formally derived and modelled function with the function generated by the real structure must be ensured. In addition, the modelled function must exhibit a behavior that is equal to the function to be realized. In this article, a structure-preserving verification method is at first presented, and illustrated with a real digital circuit by verifying the circuit and respectively testing it for known, self-injected faults. The results are displayed as signal flow graphs by means of self-written program codes.