Pub Date : 2017-07-03DOI: 10.1109/IMS3TW.2017.7995205
S. David-Grignot, Achraf Lamlih, V. Kerzérho, F. Azais, F. Soulier, S. Bernard, T. Rouyer, S. Bonhommeau
On-chip sine-wave signal generation is widely covered by literature for Built-In-Self Test (BIST) or biosensor applications. The objective is to generate pure and robust sinewave signal with minimal hardware resources. An attractive solution consists in combining several digital signals to built this analog sine-wave. The objective of this paper is to give an analytical study of various potential solutions based on digitalbased approaches. Thanks to this study, we prove that technique consisting in setting the phase shifts and various amplitude values of the square-wave signals is the most efficient approach. Moreover, this study allows the selection of the best solution in terms of parameters of the square-wave signals to cancel loworder harmonics of the generated signal.
{"title":"Analytical study of on-chip generations of analog sine-wave based on combined digital signals","authors":"S. David-Grignot, Achraf Lamlih, V. Kerzérho, F. Azais, F. Soulier, S. Bernard, T. Rouyer, S. Bonhommeau","doi":"10.1109/IMS3TW.2017.7995205","DOIUrl":"https://doi.org/10.1109/IMS3TW.2017.7995205","url":null,"abstract":"On-chip sine-wave signal generation is widely covered by literature for Built-In-Self Test (BIST) or biosensor applications. The objective is to generate pure and robust sinewave signal with minimal hardware resources. An attractive solution consists in combining several digital signals to built this analog sine-wave. The objective of this paper is to give an analytical study of various potential solutions based on digitalbased approaches. Thanks to this study, we prove that technique consisting in setting the phase shifts and various amplitude values of the square-wave signals is the most efficient approach. Moreover, this study allows the selection of the best solution in terms of parameters of the square-wave signals to cancel loworder harmonics of the generated signal.","PeriodicalId":115078,"journal":{"name":"2017 International Mixed Signals Testing Workshop (IMSTW)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123873173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IMS3TW.2017.7995209
M. Denguir, S. Sattler
When performing a separation of test results, coping with enormous high-dimensional data sets is necessary but problematic. The input of high-dimensional data, in which not a few elements are irrelevant or less relevant than others, usually lead to inadequate results. It is therefore useful to consult methods, which classify the individual dimensions of the data volumes according to their relevance. In this paper, we present the Principal Component Analysis (PCA) and a Self-developed non-linear Data Analysis (SEDA), used on a complete data collection, as classification methods. Both analyzes are clarified using the same example.
{"title":"A dimensionality-reduction method for test data","authors":"M. Denguir, S. Sattler","doi":"10.1109/IMS3TW.2017.7995209","DOIUrl":"https://doi.org/10.1109/IMS3TW.2017.7995209","url":null,"abstract":"When performing a separation of test results, coping with enormous high-dimensional data sets is necessary but problematic. The input of high-dimensional data, in which not a few elements are irrelevant or less relevant than others, usually lead to inadequate results. It is therefore useful to consult methods, which classify the individual dimensions of the data volumes according to their relevance. In this paper, we present the Principal Component Analysis (PCA) and a Self-developed non-linear Data Analysis (SEDA), used on a complete data collection, as classification methods. Both analyzes are clarified using the same example.","PeriodicalId":115078,"journal":{"name":"2017 International Mixed Signals Testing Workshop (IMSTW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130644559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IMS3TW.2017.7995200
G. Léger, A. Ginés
This paper builds upon recent developments that argue for a fault simulation based on defect-likelihood sampling. It first questions, with a number of synthetic experiments, the premises of this approach and offers an alternative simple mechanism for the random selection of defects. Then, it introduces a new layer of variability with the parametrization of the opens and shorts resistivity while keeping the computational cost overhead low by means of an adaptive strategy.
{"title":"Likelihood-sampling adaptive fault simulation","authors":"G. Léger, A. Ginés","doi":"10.1109/IMS3TW.2017.7995200","DOIUrl":"https://doi.org/10.1109/IMS3TW.2017.7995200","url":null,"abstract":"This paper builds upon recent developments that argue for a fault simulation based on defect-likelihood sampling. It first questions, with a number of synthetic experiments, the premises of this approach and offers an alternative simple mechanism for the random selection of defects. Then, it introduces a new layer of variability with the parametrization of the opens and shorts resistivity while keeping the computational cost overhead low by means of an adaptive strategy.","PeriodicalId":115078,"journal":{"name":"2017 International Mixed Signals Testing Workshop (IMSTW)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126654170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IMS3TW.2017.7995203
A. Gebregiorgis, M. Tahoori
Energy reduction has become an important issue in the design of battery-powered devices for Internet of Things (IoT) applications. In this regard, lowering the supply voltage close to transistor threshold voltage, commonly known as Near Threshold Computing (NTC), has been a widely used approach to reduce the energy consumption of various designs. However, the energy-saving potential of NTC is hindered by various factors such as variation-induced functional failures of caches. To address this issue and get utmost NTC benefits, we provide a comprehensive analysis of memory failure mechanisms and propose proper mitigation scheme for near threshold caches. In this work, aging and variation-induced memory failures are analyzed first by incorporating device and circuit level models. Afterwards, we employ Built-in Self- Test (BIST) to identify the lowest voltage limit at which each memory block can properly operate. Then, a mitigation scheme is developed by disabling unreliable portion of the cache and mapping their accesses to the reliable portion. Our evaluation using 16KByte cache shows the proposed mitigation scheme can effectively address permanent and transient memory failures and achieve more than 30% energy-saving of near threshold caches with less than 10% reduction in effective cache size and almost negligible increase in cache miss rate.
{"title":"Reliability analysis and mitigation of near threshold caches","authors":"A. Gebregiorgis, M. Tahoori","doi":"10.1109/IMS3TW.2017.7995203","DOIUrl":"https://doi.org/10.1109/IMS3TW.2017.7995203","url":null,"abstract":"Energy reduction has become an important issue in the design of battery-powered devices for Internet of Things (IoT) applications. In this regard, lowering the supply voltage close to transistor threshold voltage, commonly known as Near Threshold Computing (NTC), has been a widely used approach to reduce the energy consumption of various designs. However, the energy-saving potential of NTC is hindered by various factors such as variation-induced functional failures of caches. To address this issue and get utmost NTC benefits, we provide a comprehensive analysis of memory failure mechanisms and propose proper mitigation scheme for near threshold caches. In this work, aging and variation-induced memory failures are analyzed first by incorporating device and circuit level models. Afterwards, we employ Built-in Self- Test (BIST) to identify the lowest voltage limit at which each memory block can properly operate. Then, a mitigation scheme is developed by disabling unreliable portion of the cache and mapping their accesses to the reliable portion. Our evaluation using 16KByte cache shows the proposed mitigation scheme can effectively address permanent and transient memory failures and achieve more than 30% energy-saving of near threshold caches with less than 10% reduction in effective cache size and almost negligible increase in cache miss rate.","PeriodicalId":115078,"journal":{"name":"2017 International Mixed Signals Testing Workshop (IMSTW)","volume":"749 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116102767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IMS3TW.2017.7995206
A. Hatzopoulos
Although most of the integrated circuits in everyday applications surrounding us are digital, analog electronic circuits are still necessary, since the real world is analog and our human sensors and transmitters are also analog (ears, eyes, speech). Testing of these analog, mixedsignal and RF parts poses challenges quite different from those imposed by digital modules, while increasing considerably the cost of testing complex SoC. A set of analog circuit testing methods will be discussed. More specifically, the supply current testing method, the application of Wavelets and other techniques, and the classification-based testing will be described and their benefits versus the traditional specification-based test methods will be underlined.
{"title":"Analog circuit testing","authors":"A. Hatzopoulos","doi":"10.1109/IMS3TW.2017.7995206","DOIUrl":"https://doi.org/10.1109/IMS3TW.2017.7995206","url":null,"abstract":"Although most of the integrated circuits in everyday applications surrounding us are digital, analog electronic circuits are still necessary, since the real world is analog and our human sensors and transmitters are also analog (ears, eyes, speech). Testing of these analog, mixedsignal and RF parts poses challenges quite different from those imposed by digital modules, while increasing considerably the cost of testing complex SoC. A set of analog circuit testing methods will be discussed. More specifically, the supply current testing method, the application of Wavelets and other techniques, and the classification-based testing will be described and their benefits versus the traditional specification-based test methods will be underlined.","PeriodicalId":115078,"journal":{"name":"2017 International Mixed Signals Testing Workshop (IMSTW)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124574357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IMS3TW.2017.7995204
B. Gönültas, Sacid Aygün, R. Khayatzadeh, F. Çivitci, Y. D. Gökdel, M. B. Yelten, O. Ferhanoğlu
3D-printed dynamic structures have arisen as a lower cost and easier to fabricate alternative to miniaturized sensor and actuator technologies. Here, we investigate the reliability of a selected 3D-printed laser scanner, which was initially designed for miniaturized confocal imaging, having 1 x 1 cm2 footprint. The scan-line, 1st resonant frequency and quality factor of 3 devices were monitored for 100,000,000 (hundred million) cycles, and an average deviation of <6% was observed for all three parameters under investigation, for the devices under test. We conclude that 3D printed dynamic structures are promising candidates for a variety of applications, including optomedical imaging applications that demand disposable and low-cost scanning technologies.
3d打印动态结构作为一种成本更低、更容易制造的替代小型化传感器和执行器技术而出现。在这里，我们研究了选定的3d打印激光扫描仪的可靠性，该扫描仪最初设计用于小型化共聚焦成像，占地面积为1 x 1 cm2。对3个设备的扫描线、第一共振频率和质量因子进行了100,000,000(1亿)个周期的监测，在被测设备中，所有被测设备的三个参数的平均偏差<6%。我们得出的结论是，3D打印动态结构是各种应用的有希望的候选者，包括需要一次性和低成本扫描技术的光学成像应用。
{"title":"Reliability of 3D-printed dynamic scanners","authors":"B. Gönültas, Sacid Aygün, R. Khayatzadeh, F. Çivitci, Y. D. Gökdel, M. B. Yelten, O. Ferhanoğlu","doi":"10.1109/IMS3TW.2017.7995204","DOIUrl":"https://doi.org/10.1109/IMS3TW.2017.7995204","url":null,"abstract":"3D-printed dynamic structures have arisen as a lower cost and easier to fabricate alternative to miniaturized sensor and actuator technologies. Here, we investigate the reliability of a selected 3D-printed laser scanner, which was initially designed for miniaturized confocal imaging, having 1 x 1 cm2 footprint. The scan-line, 1st resonant frequency and quality factor of 3 devices were monitored for 100,000,000 (hundred million) cycles, and an average deviation of <6% was observed for all three parameters under investigation, for the devices under test. We conclude that 3D printed dynamic structures are promising candidates for a variety of applications, including optomedical imaging applications that demand disposable and low-cost scanning technologies.","PeriodicalId":115078,"journal":{"name":"2017 International Mixed Signals Testing Workshop (IMSTW)","volume":"148 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125873896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IMS3TW.2017.7995207
Sabyasachi Deyati, B. Muldrey, A. Singh, A. Chatterjee
Alternative signature based testing of analog/RF circuits and systems has been established over the last two decades. Signature based testing is predicated on signature from device under test (DUT) to statistically predict specifications of an IC. Statistical correlation between specifications and signature are built from a set of initial ICs. Aliasing in signature space will produce aliasing in specification space and lead to incorrect specification prediction. Alternate test aims to create unique IC specific signature to avoid aliasing. Hardware security also entails a unique signature from the device to be authenticated. Theories and infrastructure build for alternative testing of analog/RF circuits can be leveraged to design analog security primitives (analog PUFs) for hardware security. In this paper we will focus on how the alternative signature test infrastructure can be extended to hardware security.
{"title":"Design of efficient analog physically unclonable functions using alternative test principles","authors":"Sabyasachi Deyati, B. Muldrey, A. Singh, A. Chatterjee","doi":"10.1109/IMS3TW.2017.7995207","DOIUrl":"https://doi.org/10.1109/IMS3TW.2017.7995207","url":null,"abstract":"Alternative signature based testing of analog/RF circuits and systems has been established over the last two decades. Signature based testing is predicated on signature from device under test (DUT) to statistically predict specifications of an IC. Statistical correlation between specifications and signature are built from a set of initial ICs. Aliasing in signature space will produce aliasing in specification space and lead to incorrect specification prediction. Alternate test aims to create unique IC specific signature to avoid aliasing. Hardware security also entails a unique signature from the device to be authenticated. Theories and infrastructure build for alternative testing of analog/RF circuits can be leveraged to design analog security primitives (analog PUFs) for hardware security. In this paper we will focus on how the alternative signature test infrastructure can be extended to hardware security.","PeriodicalId":115078,"journal":{"name":"2017 International Mixed Signals Testing Workshop (IMSTW)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125674435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IMS3TW.2017.7995208
M. Denguir, S. Sattler
For the verification and functional safety of real systems, e.g. of analog and digital circuits, the function associated with the real structure must be modelled with structural integrity ensured. This means that the consistency of the formally derived and modelled function with the function generated by the real structure must be ensured. In addition, the modelled function must exhibit a behavior that is equal to the function to be realized. In this article, a structure-preserving verification method is at first presented, and illustrated with a real digital circuit by verifying the circuit and respectively testing it for known, self-injected faults. The results are displayed as signal flow graphs by means of self-written program codes.
{"title":"Verification and test of real circuits","authors":"M. Denguir, S. Sattler","doi":"10.1109/IMS3TW.2017.7995208","DOIUrl":"https://doi.org/10.1109/IMS3TW.2017.7995208","url":null,"abstract":"For the verification and functional safety of real systems, e.g. of analog and digital circuits, the function associated with the real structure must be modelled with structural integrity ensured. This means that the consistency of the formally derived and modelled function with the function generated by the real structure must be ensured. In addition, the modelled function must exhibit a behavior that is equal to the function to be realized. In this article, a structure-preserving verification method is at first presented, and illustrated with a real digital circuit by verifying the circuit and respectively testing it for known, self-injected faults. The results are displayed as signal flow graphs by means of self-written program codes.","PeriodicalId":115078,"journal":{"name":"2017 International Mixed Signals Testing Workshop (IMSTW)","volume":"296 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123080528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/IMS3TW.2017.7995201
Hani Malloug, M. Barragán, S. Mir, H. L. Gall
Harmonic cancelation strategies have been proposed as a promising solution for the implementation of accurate onchip sinusoidal signal generators while minimizing the required on-chip resources. Harmonic cancelation-based generators can be implemented using digital resources to provide a set of phaseshifted digital square-wave signals and a summing network built with passive or active components for scaling and combining these phase-shifted signals. The practical implementation of the scaling weight ratios for the different phased-shifted signals is a critical aspect of the harmonic cancelation strategy. Indeed, small variations between these weights due to mismatch and process variations will reduce the effectiveness of the technique and increase the magnitude of undesired harmonic components. In this work, different harmonic cancelation strategies are presented and analyzed with the goal of simplifying the onchip implementation of the scaling weights. Statistical behavioral simulations are provided in order to demonstrate the feasibility of the proposed approach.
{"title":"Harmonic cancelation strategies for on-chip sinusoidal signal generation using digital resources","authors":"Hani Malloug, M. Barragán, S. Mir, H. L. Gall","doi":"10.1109/IMS3TW.2017.7995201","DOIUrl":"https://doi.org/10.1109/IMS3TW.2017.7995201","url":null,"abstract":"Harmonic cancelation strategies have been proposed as a promising solution for the implementation of accurate onchip sinusoidal signal generators while minimizing the required on-chip resources. Harmonic cancelation-based generators can be implemented using digital resources to provide a set of phaseshifted digital square-wave signals and a summing network built with passive or active components for scaling and combining these phase-shifted signals. The practical implementation of the scaling weight ratios for the different phased-shifted signals is a critical aspect of the harmonic cancelation strategy. Indeed, small variations between these weights due to mismatch and process variations will reduce the effectiveness of the technique and increase the magnitude of undesired harmonic components. In this work, different harmonic cancelation strategies are presented and analyzed with the goal of simplifying the onchip implementation of the scaling weights. Statistical behavioral simulations are provided in order to demonstrate the feasibility of the proposed approach.","PeriodicalId":115078,"journal":{"name":"2017 International Mixed Signals Testing Workshop (IMSTW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129187021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：