A 5Gb/s equalizer for USB 3.0 receiver in 65 nm CMOS technology

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2011-04-13 DOI:10.1109/DDECS.2011.5783063

Jakub Kopanski, W. Pleskacz, D. Pienkowski

引用次数: 3

Abstract

In this paper a 5Gb/s equalizer has been presented. It is designed to operate within USB 3.0 transceiver and compensates for frequency dependent losses introduced by transmission channel. For the reference signal, the clock and data recovery circuit has been used. This approach allowed to minimize the equalizer components. Critical equalizer building blocks have been implemented in GLOBALFOUNDRIES 65 nm Low Power CMOS technology. Other blocks are modeled in hardware description language. Mixed-signal system simulation results show full functionality of the proposed solution.

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基于65nm CMOS技术的USB 3.0接收器5Gb/s均衡器

本文提出了一种5Gb/s的均衡器。它被设计为在USB 3.0收发器内工作，并补偿由传输通道引入的频率相关损失。参考信号采用时钟和数据恢复电路。这种方法允许最小化均衡器组件。关键均衡器构建模块已在GLOBALFOUNDRIES 65纳米低功耗CMOS技术中实现。其他模块用硬件描述语言建模。混合信号系统仿真结果表明了所提出的解决方案的完整功能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

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