Characterization of Plastic Packages Using (100) Silicon Stress Test Chips

Abstract

In this work, special (100) test chips containing optimized four element dual polarity rosettes have been applied within several plastic encapsulated electronic packaging configurations. The utilized test chips are capable of evaluating four stress components, and both the in-plane normal stress difference and the in-plane shear stress can be measured in a temperature compensated manner. In this paper, results are reported for test chips encapsulated in 44 pin PLCC packages. The pre and post packaging room temperature resistances of the sensors were recorded. Using the measured resistance changes and the appropriate theoretical equations, the stresses on the surface of the die were then calculated. Also, three-dimensional nonlinear finite element simulations of the plastic encapsulated packages were performed. The experimental results are in reasonable agreement with the finite element predictions, given the limitations of the constitutive models used in the numerical calculations.