Optimizing DCNN FPGA accelerator design for handwritten hangul character recognition: work-in-progress

Abstract

Deep1 Convolutional Neural Network (DCNN) is a break-through technology in image recognition. However, because of extreme computing resource requirements, DCNN need to be implemented by hardware accelerator. In this paper, we present an FPGA-based accelerator design techniques of DCNN for handwritten Hangul character recognition engine. We achieved about 11.9ms recognition time per character with Xilinx FPGA accelerator. Our design optimization was performed with Xilinx HLS and SDAccel environment targeting Kintex XCKU115 FPGA from Xilinx. Our design outperforms CPU in terms of execution time 6.25 times, and GPGPU in terms of energy efficiency 4.7 times and cooling cost for the computing servers by 17 times. We think the research results imply deep learning with FPGA accelerator will be alternative to GPGPU solutions for real-time applications, especially in data centers or sever farms.