Chaofan Li, Deepashree Sengupta, F. S. Snigdha, Wenbin Xu, Jiang Hu, S. Sapatnekar
Approximate computing has applications in areas such as image processing, neural computation, distributed systems, and real-time systems, where the results may be acceptable in the presence of controlled levels of error. The promise of approximate computing is in its ability to render just enough performance to meet quality constraints. However, going from this theoretical promise to a practical implementation requires a clear comprehension of the system requirements and matching them to the design of approximations as the system is implemented. This involves the tasks of (a) identifying the design space of potential approximations, (b) modeling the injected error as a function of the level of approximation, and (c) optimizing the system over the design space to maximize a metric, typically the power savings, under constraints on the maximum allowable degradation. Often, the error may be introduced at a low level of design (e.g., at the level of a full adder) but its impact must be percolated up to system-level error metrics (e.g., PSNR in a compressed image), and a practical approach must devise a coherent and quantifiable way of translating between error/power tradeoffs at all levels of design.
{"title":"A quantifiable approach to approximate computing: special session","authors":"Chaofan Li, Deepashree Sengupta, F. S. Snigdha, Wenbin Xu, Jiang Hu, S. Sapatnekar","doi":"10.1145/3125501.3125511","DOIUrl":"https://doi.org/10.1145/3125501.3125511","url":null,"abstract":"Approximate computing has applications in areas such as image processing, neural computation, distributed systems, and real-time systems, where the results may be acceptable in the presence of controlled levels of error. The promise of approximate computing is in its ability to render just enough performance to meet quality constraints. However, going from this theoretical promise to a practical implementation requires a clear comprehension of the system requirements and matching them to the design of approximations as the system is implemented. This involves the tasks of (a) identifying the design space of potential approximations, (b) modeling the injected error as a function of the level of approximation, and (c) optimizing the system over the design space to maximize a metric, typically the power savings, under constraints on the maximum allowable degradation. Often, the error may be introduced at a low level of design (e.g., at the level of a full adder) but its impact must be percolated up to system-level error metrics (e.g., PSNR in a compressed image), and a practical approach must devise a coherent and quantifiable way of translating between error/power tradeoffs at all levels of design.","PeriodicalId":259093,"journal":{"name":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122610546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
JavaScript1 is heavily used in the web, yet it is much slower than other languages. To improve the JavaScript performance, ahead-of-time compilation (AOTC) has been used, either to reuse the bytecode or the machine code generated by the baseline just-in-time compilation (JITC). JavaScript engines today employ high-performance optimizing JITC. So, we propose an AOTC that reuses the code generated by the optimizing JITC. It is more challenging than existing AOTCs since we need to handle more complex address relocation issues. Our preliminary evaluation shows that the proposed AOTC is promising, though.
{"title":"Advanced ahead-of-time compilation for Javascript engine: work-in-progress","authors":"Hyukwoo Park, SungKook Kim, Soo-Mook Moon","doi":"10.1145/3125501.3125512","DOIUrl":"https://doi.org/10.1145/3125501.3125512","url":null,"abstract":"JavaScript1 is heavily used in the web, yet it is much slower than other languages. To improve the JavaScript performance, ahead-of-time compilation (AOTC) has been used, either to reuse the bytecode or the machine code generated by the baseline just-in-time compilation (JITC). JavaScript engines today employ high-performance optimizing JITC. So, we propose an AOTC that reuses the code generated by the optimizing JITC. It is more challenging than existing AOTCs since we need to handle more complex address relocation issues. Our preliminary evaluation shows that the proposed AOTC is promising, though.","PeriodicalId":259093,"journal":{"name":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130548967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. S. Moghaddam, B. Harris, Duseok Kang, Inpyo Bae, Euiseok Kim, Hyemi Min, Hansu Cho, Sukjin Kim, Bernhard Egger, S. Ha, Kiyoung Choi
This paper presents a convolutional neural network architecture that supports transfer learning for user customization. The architecture consists of a large basic inference engine and a small augmenting engine. Initially, both engines are trained using a large dataset. Only the augmenting engine is tuned to the user-specific dataset. To preserve the accuracy for the original dataset, the novel concept of quality factor is proposed. The final network is evaluated with the Caffe framework, and our own implementation on a coarse-grained reconfigurable array (CGRA) processor. Experiments with MNIST, NIST'19, and our user-specific datasets show the effectiveness of the proposed approach and the potential of CGRAs as DNN processors.
{"title":"Incremental training of CNNs for user customization: work-in-progress","authors":"M. S. Moghaddam, B. Harris, Duseok Kang, Inpyo Bae, Euiseok Kim, Hyemi Min, Hansu Cho, Sukjin Kim, Bernhard Egger, S. Ha, Kiyoung Choi","doi":"10.1145/3125501.3125519","DOIUrl":"https://doi.org/10.1145/3125501.3125519","url":null,"abstract":"This paper presents a convolutional neural network architecture that supports transfer learning for user customization. The architecture consists of a large basic inference engine and a small augmenting engine. Initially, both engines are trained using a large dataset. Only the augmenting engine is tuned to the user-specific dataset. To preserve the accuracy for the original dataset, the novel concept of quality factor is proposed. The final network is evaluated with the Caffe framework, and our own implementation on a coarse-grained reconfigurable array (CGRA) processor. Experiments with MNIST, NIST'19, and our user-specific datasets show the effectiveness of the proposed approach and the potential of CGRAs as DNN processors.","PeriodicalId":259093,"journal":{"name":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129301688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Amrouch, P. Krishnamurthy, Naman Patel, J. Henkel, R. Karri, F. Khorrami
This paper addresses two reliability-based security threats and mitigations for embedded systems namely, aging and thermal side channels. Device aging can be used as a hardware attack vector by using voltage scaling or specially crafted instruction sequences to violate embedded processor guard bands. Short-term aging effects can be utilized to cause transient degradation of the embedded device without leaving any trace of the attack. (Thermal) side channels can be used as an attack vector and as a defense. Specifically, thermal side channels are an effective and secure way to remotely monitor code execution on an embedded processor and/or to possibly leak information. Although various algorithmic means to detect anomaly are available, machine learning tools are effective for anomaly detection. We will show such utilization of deep learning networks in conjunction with thermal side channels to detect code injection/modification representing anomaly.
{"title":"Emerging (un-)reliability based security threats and mitigations for embedded systems: special session","authors":"H. Amrouch, P. Krishnamurthy, Naman Patel, J. Henkel, R. Karri, F. Khorrami","doi":"10.1145/3125501.3125529","DOIUrl":"https://doi.org/10.1145/3125501.3125529","url":null,"abstract":"This paper addresses two reliability-based security threats and mitigations for embedded systems namely, aging and thermal side channels. Device aging can be used as a hardware attack vector by using voltage scaling or specially crafted instruction sequences to violate embedded processor guard bands. Short-term aging effects can be utilized to cause transient degradation of the embedded device without leaving any trace of the attack. (Thermal) side channels can be used as an attack vector and as a defense. Specifically, thermal side channels are an effective and secure way to remotely monitor code execution on an embedded processor and/or to possibly leak information. Although various algorithmic means to detect anomaly are available, machine learning tools are effective for anomaly detection. We will show such utilization of deep learning networks in conjunction with thermal side channels to detect code injection/modification representing anomaly.","PeriodicalId":259093,"journal":{"name":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130748706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Popular application domains such as multimedia processing, machine learning, and big-data analytics operate on inherently noisy data and make decisions under uncertainty. While these applications are often good candidates for both algorithmic and system-level approximation, a major open challenge is how to analyze the influence of noisy data and candidate approximations on the application's outputs. At the same time, probabilistic programming languages provide an intuitive way to model uncertainty by expressing complex probabilistic models as computer programs. The talk will give an overview of PSI (http://www.psisolver.org), a system for exact symbolic inference. PSI computes succinct symbolic representations of the joint posterior distribution represented by a probabilistic program using static analysis. PSI supports programs with both discrete and continuous distributions. It can compute answers to various posterior distribution queries, expectation queries and assertion queries using its own back-end for symbolic reasoning. This talk will present how we can represent some problems in approximate computing as probabilistic programs and use PSI to automatically get symbolic expressions that represent the distributions of the output error.
{"title":"Probabilistic reasoning for analysis of approximate computations","authors":"Sasa Misailovic","doi":"10.1145/3125501.3125524","DOIUrl":"https://doi.org/10.1145/3125501.3125524","url":null,"abstract":"Popular application domains such as multimedia processing, machine learning, and big-data analytics operate on inherently noisy data and make decisions under uncertainty. While these applications are often good candidates for both algorithmic and system-level approximation, a major open challenge is how to analyze the influence of noisy data and candidate approximations on the application's outputs. At the same time, probabilistic programming languages provide an intuitive way to model uncertainty by expressing complex probabilistic models as computer programs. The talk will give an overview of PSI (http://www.psisolver.org), a system for exact symbolic inference. PSI computes succinct symbolic representations of the joint posterior distribution represented by a probabilistic program using static analysis. PSI supports programs with both discrete and continuous distributions. It can compute answers to various posterior distribution queries, expectation queries and assertion queries using its own back-end for symbolic reasoning. This talk will present how we can represent some problems in approximate computing as probabilistic programs and use PSI to automatically get symbolic expressions that represent the distributions of the output error.","PeriodicalId":259093,"journal":{"name":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130824237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
From voice recognition to object detection, Deep Neural Networks (DNNs) are steadily getting better at extracting information from complex raw data. Combined with the popularity of mobile computing and the rise of the Internet-of-Things (IoT), there is enormous potential for widespread deployment of intelligent devices, but a computational challenge remains. A modern DNN can require billions of floating point operations to classify a single image, which is far too costly for energy-constrained mobile devices. Offloading DNNs to powerful servers in the cloud is only a limited solution, as it requires significant energy for data transfer and cannot address applications with low-latency requirements such as augmented reality or navigation for autonomous drones.
{"title":"Towards efficient quantized neural network inference on mobile devices: work-in-progress","authors":"Yaman Umuroglu, Magnus Jahre","doi":"10.1145/3125501.3125528","DOIUrl":"https://doi.org/10.1145/3125501.3125528","url":null,"abstract":"From voice recognition to object detection, Deep Neural Networks (DNNs) are steadily getting better at extracting information from complex raw data. Combined with the popularity of mobile computing and the rise of the Internet-of-Things (IoT), there is enormous potential for widespread deployment of intelligent devices, but a computational challenge remains. A modern DNN can require billions of floating point operations to classify a single image, which is far too costly for energy-constrained mobile devices. Offloading DNNs to powerful servers in the cloud is only a limited solution, as it requires significant energy for data transfer and cannot address applications with low-latency requirements such as augmented reality or navigation for autonomous drones.","PeriodicalId":259093,"journal":{"name":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122390130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Warp-level cache bypassing has been proposed to resolve GPU memory resource contention on GPU computing. However, the proposed cache bypassing scheme has sub-optimal performance due to warp criticality problem in balanced workload. In this paper, we show that warp-level cache bypassing is a sub-optimal solution and propose a balanced cache bypassing scheme to solve this problem.
{"title":"Balanced cache bypassing for critical warp reduction: work-in-progress","authors":"Sungin Hong, Hyunjun Kim, Hwansoo Han","doi":"10.1145/3125501.3125513","DOIUrl":"https://doi.org/10.1145/3125501.3125513","url":null,"abstract":"Warp-level cache bypassing has been proposed to resolve GPU memory resource contention on GPU computing. However, the proposed cache bypassing scheme has sub-optimal performance due to warp criticality problem in balanced workload. In this paper, we show that warp-level cache bypassing is a sub-optimal solution and propose a balanced cache bypassing scheme to solve this problem.","PeriodicalId":259093,"journal":{"name":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125436640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Synchronous Dataflow Graphs (SDFGs) are widely used to model streaming applications (e.g. digital signal processing applications), which are commonly executed by embedded systems. The usage of on-chip resources is always strictly constrained in embedded systems. As the cost of instruction memory is a significant part of on-chip resource costs, code size reduction is an effective way to control the overall costs of on-chip resources. In this work, a code-size-aware mapping heuristic is proposed to decrease the code size for SDFGs on multicore systems. The mapping heuristic is jointly used with a self-timed scheduling heuristic to decrease the code size of the original schedule. In preliminary experiments, the proposed heuristic achieves significant code size reduction for all the tested SDFGs without affecting throughput.
{"title":"Code-size-aware mapping for synchronous dataflow graphs on multicore systems: work-in-progress","authors":"Mingze Ma, R. Sakellariou","doi":"10.1145/3125501.3125514","DOIUrl":"https://doi.org/10.1145/3125501.3125514","url":null,"abstract":"Synchronous Dataflow Graphs (SDFGs) are widely used to model streaming applications (e.g. digital signal processing applications), which are commonly executed by embedded systems. The usage of on-chip resources is always strictly constrained in embedded systems. As the cost of instruction memory is a significant part of on-chip resource costs, code size reduction is an effective way to control the overall costs of on-chip resources. In this work, a code-size-aware mapping heuristic is proposed to decrease the code size for SDFGs on multicore systems. The mapping heuristic is jointly used with a self-timed scheduling heuristic to decrease the code size of the original schedule. In preliminary experiments, the proposed heuristic achieves significant code size reduction for all the tested SDFGs without affecting throughput.","PeriodicalId":259093,"journal":{"name":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126318621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The automotive electronic architectures have moved from federated architectures, where one function is implemented in one ECU (Electronic Control Unit), to distributed architectures, consisting of several multicore ECUs. In addition, multicore ECUs are being adopted because of better performance, cost, size, fault-tolerance and power consumption. Automotive manufacturers use AUTomotive Open System ARchitecture (AUTOSAR) as the standardized software architecture for ECUs. With AUTOSAR, the functionality is modeled as a set of software components composed of subtasks, called runnables. In this paper we propose an approach for the automatic software functionality assignment to multicore distributed architectures, implemented as a software tool. The AUTOMAP, decides: the (i) mapping of software components to multicore ECUs, (ii) the assignment of runnables to the ECU cores, (iii) the clustering of runnables into tasks and (iv) the mapping of tasks to 'OS-Applications', such that timing and mapping constraints are satisfied. AUTOMAP has been developed to handle large industrialsized use cases, fine-grained realistic mapping and timing constraints, and to produce outputs that support the system engineer in the mapping task. We have successfully evaluated AUTOMAP on several realistic use cases from Volvo Trucks.
{"title":"Towards industry strength mapping of AUTOSAR automotive functionality on multicore architectures: work-in-progress","authors":"Cosmin Avasalcai, Dhanesh Budhrani, P. Pop","doi":"10.1145/3125501.3125623","DOIUrl":"https://doi.org/10.1145/3125501.3125623","url":null,"abstract":"The automotive electronic architectures have moved from federated architectures, where one function is implemented in one ECU (Electronic Control Unit), to distributed architectures, consisting of several multicore ECUs. In addition, multicore ECUs are being adopted because of better performance, cost, size, fault-tolerance and power consumption. Automotive manufacturers use AUTomotive Open System ARchitecture (AUTOSAR) as the standardized software architecture for ECUs. With AUTOSAR, the functionality is modeled as a set of software components composed of subtasks, called runnables. In this paper we propose an approach for the automatic software functionality assignment to multicore distributed architectures, implemented as a software tool. The AUTOMAP, decides: the (i) mapping of software components to multicore ECUs, (ii) the assignment of runnables to the ECU cores, (iii) the clustering of runnables into tasks and (iv) the mapping of tasks to 'OS-Applications', such that timing and mapping constraints are satisfied. AUTOMAP has been developed to handle large industrialsized use cases, fine-grained realistic mapping and timing constraints, and to produce outputs that support the system engineer in the mapping task. We have successfully evaluated AUTOMAP on several realistic use cases from Volvo Trucks.","PeriodicalId":259093,"journal":{"name":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","volume":"2645 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131305334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hanwool Park, Changdae Lee, Hakkyung Lee, Yechan Yoo, Yoonjin Park, Injung Kim, Kang Yi
Deep1 Convolutional Neural Network (DCNN) is a break-through technology in image recognition. However, because of extreme computing resource requirements, DCNN need to be implemented by hardware accelerator. In this paper, we present an FPGA-based accelerator design techniques of DCNN for handwritten Hangul character recognition engine. We achieved about 11.9ms recognition time per character with Xilinx FPGA accelerator. Our design optimization was performed with Xilinx HLS and SDAccel environment targeting Kintex XCKU115 FPGA from Xilinx. Our design outperforms CPU in terms of execution time 6.25 times, and GPGPU in terms of energy efficiency 4.7 times and cooling cost for the computing servers by 17 times. We think the research results imply deep learning with FPGA accelerator will be alternative to GPGPU solutions for real-time applications, especially in data centers or sever farms.
{"title":"Optimizing DCNN FPGA accelerator design for handwritten hangul character recognition: work-in-progress","authors":"Hanwool Park, Changdae Lee, Hakkyung Lee, Yechan Yoo, Yoonjin Park, Injung Kim, Kang Yi","doi":"10.1145/3125501.3125522","DOIUrl":"https://doi.org/10.1145/3125501.3125522","url":null,"abstract":"Deep1 Convolutional Neural Network (DCNN) is a break-through technology in image recognition. However, because of extreme computing resource requirements, DCNN need to be implemented by hardware accelerator. In this paper, we present an FPGA-based accelerator design techniques of DCNN for handwritten Hangul character recognition engine. We achieved about 11.9ms recognition time per character with Xilinx FPGA accelerator. Our design optimization was performed with Xilinx HLS and SDAccel environment targeting Kintex XCKU115 FPGA from Xilinx. Our design outperforms CPU in terms of execution time 6.25 times, and GPGPU in terms of energy efficiency 4.7 times and cooling cost for the computing servers by 17 times. We think the research results imply deep learning with FPGA accelerator will be alternative to GPGPU solutions for real-time applications, especially in data centers or sever farms.","PeriodicalId":259093,"journal":{"name":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123139800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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