A Robust 0.15/spl mu/m CMOS Technology With CoSi/sub 2/ Salicide And Shallow Trench Isolation

Abstract

A high performance robust 0.1 Spm CMOS technology is reported. This technology integrates two key processes including (1) a CoSi2 salicide process that realizes higher driving current than TiSi2 process and (2) a newly developed shallow trench isolation (STI) process with suppressed reverse narrow channel effect. The excellent thermal stability of sheet resistance is provided using high temperature sputtered and in-situ annealed CoSi2 salicide. In this process, 12%(PMOS) and 4%(NMOS) higher driving current have been achieved, and the VT has not been lowered down to 0.2pm channel width. The 1 8 . 5 ~ ~ Tpd has been obtained for an inverter at V ~ o = l . 8 V . Introduction Salicide and STI technologies are indispensable to 0.1.5pm CMOS and beyond. However, there are serious problems for low power application described as follows: 1) In TiSi, salicide CMOS, the driving current of PMOS is degraded by the high contact resistance on p+ diffusion layer caused by large bamer height at the silicide/Si interface. The driving current of NMOS is also degraded because of the thick gate depletion layer in nf gate poly Si caused by relatively low arsenic concentration for stable TiSi2 formation. Some techniques, for example, the elevated S/D [ l ] or the high gate doping prior gate patterning [2] can overcome these problems, but these techniques result in the increase of process steps or complexity. 2) In STI, the reverse narrow channel effect [3] increases a standby power dissipation and results in difficulties for design of embedded memory devices, regardless of its advantages for scaled isolation and low parasitic capacitance. In this paper we have demonstrated the advantage of CoSi2 on driving current of MOSFET and a newly developed STI process featuring by boron implantation into trench side wall for the suppression of reverse narrow channel effect. Design Concept 1) Improvement in driving current in a simple process CoSi2 is promising material to overcome the abovementioned TiSi2 issues, because it has a lower bamer height for p' diffusion and stable sheet resistance at high arsenic concentration compared with TiSi2 [4]. Therefore CoSi2 can allow simultaneous high dose ion implantation for gate and S D doping. 2) Shallow trench isolation The reverse narrow channel effect of NMOS with STI may be caused by boron depletion at the trench edge, which would be caused during the following process such as S/D annealing. Therefore, oblique angle boron ion implantation into the trench side wall of NMOS is used before trench filling as shown in Fig. 1. Experiment A 300nm Trench was formed with rounded corners. Boron was implanted into the trench side wall at 30 degree angle at 20keV, 2 E 1 3 ~ m ~ . STI was completed by CVD oxide filling and CMP planarization. Tub, channel, 4nm gate oxide, gate electrode were formed, followed by drain extension and pocket ion implantation for NMOS. After 50nm side wall spacer formation, ion im lantation (As: 3 E 1 5 ~ m . ~ at 5OkeV out for gate and S/D doping, followed by RTA at IOOOC for 10 sec. A single drain with pocket was used for PMOS. Furthermore, 30nm CoSi2 was formed on the S/D and gate electrode by simple salicide process using CO high temperature sputtering and in-situ vacuum annealing [4]. Results and Discussion The contact resistance of CoSi2/p' diffusion is 1/10 that of TiSi2/p' for a junction depth of 0.1.5pm (Fig.2). This low contact resistance results in 12% improvement in drain current for PMOS(Tab1e 1). To keep the IOW sheet resistance and gate depletion, CoSi2 can use single dosage (3E1.5 cm-2) for both gate poly Si and S D , although TiSi2 needs the different As dosage combination for gate (3E1.5 cm-2) and S/D(2E15 cm-*) (Table 2). Therefore, CoSi2 contributes to the increase (4%) of driving current of NMOS (Table 1) in the simple process. Since the leakage of n' and p+ junctions with CoSi2 does not scatter (Fig.3), CoSi2 spiking is not occurring. The sheet resistance of CoSi2 is <8ohm/sq. down to 0.13ym line width, even after 700C 1 hour annealing (Fig.4). These stable characteristics of Cos& are due to the uniform silicide layer as shown in Photo2 and epitaxial interface on Si [SI. STI realizes sufficient threshold voltage of parasitic field transistor and desirable structure at 0.2pm isolation width (Fig.5, Photol). The reverse narrow channel effect with STI is completely eliminated in NMOS down to 0.2" channel width, by the trench side boron implantation (Fig.6). The subthreshold slope of NMOS with trench side implantation is almost constant (-80mV/dec.) at channel width of 0.2pm to lOpm (Fig.7). 'Kink' effect in subthreshold characteristics is not observed (Fig.7,8). Implanted boron successfully suppresses VT lowering at the trench edge. In PMOS, no threshold voltage shift was observed, even without trench side implantation. Under 1.8V operation, the drain currents are 53.5 and 265pNpm for NMOS and PMOS, respectively, at hAE=0.15pm (Fig.8,9). The DIBL for NE'MOS is still small even at hATE=O.I5pm, as shown in Fig.10. The NMOS lifetime of > I O years is estimated from HC test(Fig.11). A propagation delay time of 1 8 . 5 ~ s is obtained at 1.8V power supply from ring oscillator evaluation (Fig.1 2). Conclusion A manufacturable 0.15pm CMOS process has been presented. CoSi2 salicide has successfully improved the driving current in the 0.1.5pm generation, without increase in process complexity. STI has achieved 0.20pm L/S field feature size with no reverse narrow channel effect. [ l ] H. Kotaki et al., IEDM Tech. Dig., p839 (1993). [2] M. Rodder et al., IEDM Tech. Dig., p563(1996). [3] A.H. Perera et al., IEDM Tech. Dig., p679 (1995). [4] K. Inoue et al., IEDM Tech. Dig., p445(199.5). [5] K. Inoue et al., MRS Symp. Proc., to be published [6] W. T. Lynch et al., IEDM Tech. Dig.,p3.52(1988). for NMOS, BF2: 3E15cm I: at 20keV for PMOS) were carried