Completely self-synchronous 1024-bit RSA crypt-engine in 40nm CMOS

Abstract

We have designed and measured completely self-synchronous 1024-bit RSA crypt-engine, fabricated in 40nm CMOS. We have implemented two modular exponentiation algorithms, the high-to-low(HTL) and Montgomery power ladder(MPL) in order to show the performance of the self-synchronous, gate-level pipelined architectures. Both implementations employ identical data-paths and take 804k transistors, with only difference in controller, and two interleaved 1024b cryptographic operations take from 6.1ms to 3.1ms for HTL and 6.0ms for MPL, at nominal power supply of 1.1V.