{"title":"A 15V operated Shallow Trench IGBT(ST-IGBT) fabricated by low temperature process and optimized for 12inch wafers","authors":"Masahiro Tanaka, N. Abe, A. Nakagawa","doi":"10.1109/ISPSD57135.2023.10147646","DOIUrl":null,"url":null,"abstract":"In this paper, we propose shallow trench IGBT (ST -IGBT) and its fabrication process. It is designed for 15V of gate operation, as is the same as conventional IGBTs. The cell is consist of shallow trench gate MOS structure and shallow doping layers, formed by ion implantation and RTA (Rapid Thermal Anneal). The edge termination structure is composed by many shallow FLRs. The optimized cell design reduces V ce(sat) by 0.2V, compared with conventional IGBTs.","PeriodicalId":344266,"journal":{"name":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD57135.2023.10147646","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, we propose shallow trench IGBT (ST -IGBT) and its fabrication process. It is designed for 15V of gate operation, as is the same as conventional IGBTs. The cell is consist of shallow trench gate MOS structure and shallow doping layers, formed by ion implantation and RTA (Rapid Thermal Anneal). The edge termination structure is composed by many shallow FLRs. The optimized cell design reduces V ce(sat) by 0.2V, compared with conventional IGBTs.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
