Design Space Exploration of a 512KB STT-Assisted SOT MRAM Cache

Abstract

The effects of varying the Spin Transfer Torque (STT) and Spin Orbit Torque (SOT) currents in a 512KB STT-Assisted SOT MRAM cache to its total cache area, write latency and energy consumption were investigated. The lowest cache write latencies can be achieved when the transistor widths are approximately equal. Out of all transistor sizings, the lowest write latency is 2.95ns with a corresponding cache area of 2.2756mm2. Meanwhile the lowest energy consumption is 441.777 pJ which is when the transistor widths are at their minimum.