Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333036
Soyeon Choi, Jieun Yeo, Hoyoung Yoo
Recently, many researches have investigated efficient reverse engineering methods to restore Programmable Logic Points (PLPs) and Programmable Interconnect Points (PIPs) in SRAM-based Field Programmable Gate Arrays (FPGAs). However, the research on the restoration of Programmable Content Points (PCPs) such as memory data are rarely studied. In this paper, we propose an efficient reverse engineering method to recover Read Only Memory (ROM) data, which is essential for the implementation of modern digital circuits. First, we analyze the FPGA hardware resources mapped to Xilinx primitive library of ROM, and next the proposed reverse engineering process is explained using mapping relation between ROM data and hardware resources. As an example, XC3S50 FPGA of Xilinx Sparatan-3 family is utilized, and the process of restoring the SBOX of AES (Advanced Encryption Standard) is provided as a practical application.
{"title":"Extraction of ROM Data from Bitstream in Xilinx FPGA","authors":"Soyeon Choi, Jieun Yeo, Hoyoung Yoo","doi":"10.1109/ISOCC50952.2020.9333036","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333036","url":null,"abstract":"Recently, many researches have investigated efficient reverse engineering methods to restore Programmable Logic Points (PLPs) and Programmable Interconnect Points (PIPs) in SRAM-based Field Programmable Gate Arrays (FPGAs). However, the research on the restoration of Programmable Content Points (PCPs) such as memory data are rarely studied. In this paper, we propose an efficient reverse engineering method to recover Read Only Memory (ROM) data, which is essential for the implementation of modern digital circuits. First, we analyze the FPGA hardware resources mapped to Xilinx primitive library of ROM, and next the proposed reverse engineering process is explained using mapping relation between ROM data and hardware resources. As an example, XC3S50 FPGA of Xilinx Sparatan-3 family is utilized, and the process of restoring the SBOX of AES (Advanced Encryption Standard) is provided as a practical application.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124435112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332953
Jooyong Choi, Suk-ju Kang, Minjoo Lee, Jun-Young Park, Jiwoong Lee
In this paper, we propose a novel sequential compression method for the coefficient look-up table (LUT) for compensation of display panel defects. First, the regression LUT coefficient data for defect compensation is rearranged as the display ratio. It is split and compressed into sub-blocks to utilize the correlation of the rearranged data. Then, to further increase the compression ratio, the initially compressed data is compressed again through the differential coding-based compression. In the performance evaluation, the proposed method has the same loss as the existing compression method, while increasing the compression ratio of up to 46.9%.
{"title":"Sequential Compression Using Efficient LUT Correlation for Display Defect Compensation","authors":"Jooyong Choi, Suk-ju Kang, Minjoo Lee, Jun-Young Park, Jiwoong Lee","doi":"10.1109/ISOCC50952.2020.9332953","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332953","url":null,"abstract":"In this paper, we propose a novel sequential compression method for the coefficient look-up table (LUT) for compensation of display panel defects. First, the regression LUT coefficient data for defect compensation is rearranged as the display ratio. It is split and compressed into sub-blocks to utilize the correlation of the rearranged data. Then, to further increase the compression ratio, the initially compressed data is compressed again through the differential coding-based compression. In the performance evaluation, the proposed method has the same loss as the existing compression method, while increasing the compression ratio of up to 46.9%.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127265852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332934
Dong Won Lee, Kangyoon Lee
This article presents about 5.8GHz noise cancelling CMOS LNA for DSRC communication. The LNA is designed with differential output with balun architecture and resistive-feedback noise cancelling technique. Tunable load capacitor bank achieves wideband input matching and gain selection. The LNA is implemented in 130nm CMOS technology and achieves a simulated gain of 24.2dB and PldB of -13.46dB and noise figure(NF) of 2.74dB at center frequency. The power consumption is 10.51mW at 1.2V power supply. The chip area is 509×559µm2
{"title":"A Design of 5.8GHz Tunable Band Noise Cancelling CMOS LNA for DSRC Communications","authors":"Dong Won Lee, Kangyoon Lee","doi":"10.1109/ISOCC50952.2020.9332934","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332934","url":null,"abstract":"This article presents about 5.8GHz noise cancelling CMOS LNA for DSRC communication. The LNA is designed with differential output with balun architecture and resistive-feedback noise cancelling technique. Tunable load capacitor bank achieves wideband input matching and gain selection. The LNA is implemented in 130nm CMOS technology and achieves a simulated gain of 24.2dB and PldB of -13.46dB and noise figure(NF) of 2.74dB at center frequency. The power consumption is 10.51mW at 1.2V power supply. The chip area is 509×559µm2","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123545320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332978
Younggyun Cho, Mi Lu
Due to the high demands for computing, the available resources always lack. The approximate computing technique is the key to lowering hardware complexity and improving energy efficiency and performance. However, it is a challenge to properly design approximate multipliers since input data are unseen to users. This challenge can be overcome by Machine Learning (ML) classifiers. ML classifiers can predict the detailed feature of upcoming input data. Previous approximate multipliers are designed using simple adders based on ML classifiers but by using a simple adder-based approximate multiplier, the level of approximation cannot change at runtime. To overcome this drawback, using an accumulator and reconfigurable adders instead of simple adders are proposed in this paper. Also, the rounding technique is applied to approximate floating-point multipliers for further improvement. Our experimental results show that when the error tolerance of our target application is less than 5%, the proposed approximate multiplier can save area by 70.98%, and when the error tolerance is less than 3%, a rounding enhanced simple adders-based approximate multiplier can save area by 65.9% and a reconfigurable adder-based approximate multiplier with rounding can reduce the average delay and energy by 54.95% and 46.67% respectively compared to an exact multiplier.
{"title":"A Reconfigurable Approximate Floating-Point Multiplier with kNN","authors":"Younggyun Cho, Mi Lu","doi":"10.1109/ISOCC50952.2020.9332978","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332978","url":null,"abstract":"Due to the high demands for computing, the available resources always lack. The approximate computing technique is the key to lowering hardware complexity and improving energy efficiency and performance. However, it is a challenge to properly design approximate multipliers since input data are unseen to users. This challenge can be overcome by Machine Learning (ML) classifiers. ML classifiers can predict the detailed feature of upcoming input data. Previous approximate multipliers are designed using simple adders based on ML classifiers but by using a simple adder-based approximate multiplier, the level of approximation cannot change at runtime. To overcome this drawback, using an accumulator and reconfigurable adders instead of simple adders are proposed in this paper. Also, the rounding technique is applied to approximate floating-point multipliers for further improvement. Our experimental results show that when the error tolerance of our target application is less than 5%, the proposed approximate multiplier can save area by 70.98%, and when the error tolerance is less than 3%, a rounding enhanced simple adders-based approximate multiplier can save area by 65.9% and a reconfigurable adder-based approximate multiplier with rounding can reduce the average delay and energy by 54.95% and 46.67% respectively compared to an exact multiplier.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125291767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333030
Wonjong Kim, Hyegang Jun
This paper describes a prototyping methodology for implementing deep neural network (DNN) models in hardware. From a DNN model developed in C or C++ programming language, we develop a hardware architecture using a SoC virtual platform and verify the functionality using FPGA board. It demonstrates the viability of using FPGAs for accelerating specific applications written in a high-level language. With the use of High-level Synthesis tools provided by Xilinx [3], it is shown to be possible to implement an FPGA design that would run the inference calculations required by the MobileNetV2 [1] Deep Neural Network. With minimal alterations to the C++ code developed for a software implementation of the MobileNetV2 where HDL code could be directly synthesized from the original C++ code, dramatically reducing the complexity of the project. Consequently, when the design was implemented on an FPGA, upwards of 5 times increase in speed was able to be realized when compared to similar processors (ARM7).
{"title":"Fast Prototyping of a Deep Neural Network on an FPGA","authors":"Wonjong Kim, Hyegang Jun","doi":"10.1109/ISOCC50952.2020.9333030","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333030","url":null,"abstract":"This paper describes a prototyping methodology for implementing deep neural network (DNN) models in hardware. From a DNN model developed in C or C++ programming language, we develop a hardware architecture using a SoC virtual platform and verify the functionality using FPGA board. It demonstrates the viability of using FPGAs for accelerating specific applications written in a high-level language. With the use of High-level Synthesis tools provided by Xilinx [3], it is shown to be possible to implement an FPGA design that would run the inference calculations required by the MobileNetV2 [1] Deep Neural Network. With minimal alterations to the C++ code developed for a software implementation of the MobileNetV2 where HDL code could be directly synthesized from the original C++ code, dramatically reducing the complexity of the project. Consequently, when the design was implemented on an FPGA, upwards of 5 times increase in speed was able to be realized when compared to similar processors (ARM7).","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116015265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333010
W. Choi
An effective software scheme has been proposed for implementing the space vector modulation (SVM) of the three-phase split-output inverter (SOI). The conventional SVM algorithm needs complex computations, such as square root and arctangent. The SVM proposed in this paper, is further developed to decide directly the conduction times of power switches of three-phase SOI without requiring complex computations. One-chip micro-controller has been utilized for implementing the proposed algorithm. Experimental results have verified the effectiveness of the proposed approach by designing a 1.0 kW prototype inverter system.
{"title":"Effective Software Scheme of the Space Vector Modulation Using One-Chip Micro-Controller","authors":"W. Choi","doi":"10.1109/ISOCC50952.2020.9333010","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333010","url":null,"abstract":"An effective software scheme has been proposed for implementing the space vector modulation (SVM) of the three-phase split-output inverter (SOI). The conventional SVM algorithm needs complex computations, such as square root and arctangent. The SVM proposed in this paper, is further developed to decide directly the conduction times of power switches of three-phase SOI without requiring complex computations. One-chip micro-controller has been utilized for implementing the proposed algorithm. Experimental results have verified the effectiveness of the proposed approach by designing a 1.0 kW prototype inverter system.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114387490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9332986
Jiun Hong, TaeGeon Lee, Saad Arslan, Hyungwon Kim
This paper presents a compact architecture of CNN training accelerator targeted for mobile devices. Accuracy was verified using python in the CNN structure, and accuracy was compared by applying several data types to find optimized data types. In addition, floating-point operations are used in the computation of the CNN structure, and to implemented them, we have created and verified the addition, subtraction, and multiplication circuits of floating-point. The CNN architecture was verified using python, the floating point operation was verified using Vivado, and Area was verified TSMC 180nm.
{"title":"Compact CNN Training Accelerator with Variable Floating-Point Datapath","authors":"Jiun Hong, TaeGeon Lee, Saad Arslan, Hyungwon Kim","doi":"10.1109/ISOCC50952.2020.9332986","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332986","url":null,"abstract":"This paper presents a compact architecture of CNN training accelerator targeted for mobile devices. Accuracy was verified using python in the CNN structure, and accuracy was compared by applying several data types to find optimized data types. In addition, floating-point operations are used in the computation of the CNN structure, and to implemented them, we have created and verified the addition, subtraction, and multiplication circuits of floating-point. The CNN architecture was verified using python, the floating point operation was verified using Vivado, and Area was verified TSMC 180nm.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114584967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333088
S. SunitaM., D. MayurG., Preet Bedi, Nagesh Verma, Shashidhar Tantry
This paper presents a 50MHz, 3.5V input and 0.6- 3.12V output, 3-Level Buck Converter with the inclusion of a calibration circuit to ensure a constant voltage across the flying capacitor. Additionally, a Boost Converter is designed to increase the max output voltage level to 5.8V. All the circuits and their blocks are designed and simulated in 45nm CMOS technology on Cadence virtuoso. Peak efficiency is observed to be 90.3% for 3-Level Buck Converter and 93.6% for the modified Boost Converter.
{"title":"50 MHz 3-Level Buck Converter with added Boost Converter","authors":"S. SunitaM., D. MayurG., Preet Bedi, Nagesh Verma, Shashidhar Tantry","doi":"10.1109/ISOCC50952.2020.9333088","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333088","url":null,"abstract":"This paper presents a 50MHz, 3.5V input and 0.6- 3.12V output, 3-Level Buck Converter with the inclusion of a calibration circuit to ensure a constant voltage across the flying capacitor. Additionally, a Boost Converter is designed to increase the max output voltage level to 5.8V. All the circuits and their blocks are designed and simulated in 45nm CMOS technology on Cadence virtuoso. Peak efficiency is observed to be 90.3% for 3-Level Buck Converter and 93.6% for the modified Boost Converter.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121926957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-21DOI: 10.1109/ISOCC50952.2020.9333116
K. Chen, Jing-Wen Liang
Activation function design is critical in the convolutional neural network (CNN) because it affects the learning speed and the precision of classification. In a hardware implementation, using traditional activation function may cause large hardware area overhead due to its complicated calculation such as exponential. To reduce the hardware overhead, Taylor series expansion is a popular way to approximate the traditional activation function. However, this approach brings some approximation errors, which reduce the accuracy of the involved CNN model. Therefore, the trainable activation function and a two-stage training mechanism are proposed in this paper to compensate for the accuracy loss due to the Taylor series expansion. After initializing the involved trainable activation function, the coefficients of the trainable activation function according to different neural network layer will be adjusted properly along with the neural network training process. Compared with the conventional approach, the proposed trainable activation function can involve fewer Taylor expansion terms to improve the classification accuracy by 2.24% to 53.96%. Therefore, CNN with trainable activation functions can achieve better classification accuracy with less area cost.
{"title":"A Two-stage Training Mechanism for the CNN with Trainable Activation Function","authors":"K. Chen, Jing-Wen Liang","doi":"10.1109/ISOCC50952.2020.9333116","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333116","url":null,"abstract":"Activation function design is critical in the convolutional neural network (CNN) because it affects the learning speed and the precision of classification. In a hardware implementation, using traditional activation function may cause large hardware area overhead due to its complicated calculation such as exponential. To reduce the hardware overhead, Taylor series expansion is a popular way to approximate the traditional activation function. However, this approach brings some approximation errors, which reduce the accuracy of the involved CNN model. Therefore, the trainable activation function and a two-stage training mechanism are proposed in this paper to compensate for the accuracy loss due to the Taylor series expansion. After initializing the involved trainable activation function, the coefficients of the trainable activation function according to different neural network layer will be adjusted properly along with the neural network training process. Compared with the conventional approach, the proposed trainable activation function can involve fewer Taylor expansion terms to improve the classification accuracy by 2.24% to 53.96%. Therefore, CNN with trainable activation functions can achieve better classification accuracy with less area cost.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129565592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The deep learning acceleration hardwareperformance is greatly affected by Processing Elements (PEs). In order to apply deep learning accelerators to mobile devices, optimized PE must be designed as ASIC. To improve the performance of PE, we focused on methods of minimizing external memory access and parallelization. As a result, a deep learning accelerator architecture consisting of 512 PEs in parallel is proposed and the results of FPGA implementation is presented.
为了提高PE的性能，我们关注最小化外部内存访问和并行化的方法。
{"title":"Implementation of a Round Robin Processing Element for Deep Learning Accelerator","authors":"Eunchong Lee, Yongseok Lee, Sang-Seol Lee, Byoung-Ho Choi","doi":"10.1109/ISOCC50952.2020.9333012","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333012","url":null,"abstract":"The deep learning acceleration hardwareperformance is greatly affected by Processing Elements (PEs). In order to apply deep learning accelerators to mobile devices, optimized PE must be designed as ASIC. To improve the performance of PE, we focused on methods of minimizing external memory access and parallelization. As a result, a deep learning accelerator architecture consisting of 512 PEs in parallel is proposed and the results of FPGA implementation is presented.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129342690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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