Application-Oriented Characterization of Thermally Optimized, Asymmetrical Single Chip Packages for 100 V GaN HEMTs

Abstract

Gallium nitride transistors have a smaller die area compared to silicon-based devices, which can lead to thermal challenges in high current density applications. Therefore, thermally optimized packages with a high heat spreading capability in combination with small parasitic are necessary. This work investigates the thermal performance a $7\ \mathrm{m}\Omega$, 100 V GaN HEMT in a thermally optimized single chip package with integrated RTD and compares it to the commercial counterpart. The thermal optimized package shows a significantly better transient thermal impedance resulting in a static thermal resistance of 3.1 K/W, which is a 20 % reduction in comparison to the COTS package. The integrated RTD trace has a relative reaction time of 590 ms, which is 30-fold slower in comparison to the junction temperature. To show the identical electrical behavior, although the single chip package is larger, it is compared with the commercial off-the-shelf package and a $5\ \mathrm{m}\Omega$, 100 V GaN single chip package in a 300 kHz, 48 V buck converter. Both $7\ \mathrm{m}\Omega$ versions have identical efficiencies of ≈97.5 % up to 50 A output current, slightly outperforming the $5\ \mathrm{m}\Omega$ GaN transistor. With its combination of improved thermal characteristics and low-inductance, the thermally optimized package of the GaN device offers more degrees of freedom in the design of power converter to exploit trade-offs between longer lifetime, higher temperature operation and power density.