PEAS-I: A hardware/software co-design system for ASIPs

A. Alomary, Takeharu Nakata, Y. Honma, J. Sato, N. Hikichi, M. Imai
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引用次数: 45

Abstract

The current implementation and experimental results of the PEAS-1 (practical environment for application specific integrated processor (ASIP) development - Version I) system are described. The PEAS-I system is a hardware/software co-design system for ASIP development. The input to the system is a set of application programs written in C language, an associated data set, and design constraints such as chip area and power consumption. The system generates an optimized CPU core design in the form of an HDL, as well as a set of application program development tools, such as a C compiler, assembler, and simulator. A novel method that formulates the design of an optimal instruction set using an integer programming approach is described. A tool that enables the designer to predict the chip area and performance of the design before the detailed design is completed is discussed. Application program development tools are generated in addition to the ASIP hardware design.<>
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pea - i:用于api的硬件/软件协同设计系统
本文描述了pase -1(专用集成处理器(ASIP)开发的实际环境-版本I)系统的当前实现和实验结果。pea - i系统是用于ASIP开发的硬件/软件协同设计系统。系统的输入是一组用C语言编写的应用程序,一个相关的数据集,以及芯片面积和功耗等设计约束。该系统以HDL的形式生成了优化的CPU核心设计,并提供了C编译器、汇编器、模拟器等一套应用程序开发工具。本文描述了一种利用整数规划方法设计最优指令集的新方法。讨论了在详细设计完成之前,使设计人员能够预测芯片面积和设计性能的工具。除ASIP硬件设计外,还生成了应用程序开发工具。
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