Analysis on Optimal Chip Floorplanning Considering Various Types of Decoupling Capacitors in Package PDN

Jisoo Hwang, James Jeong, Heejung Choi, Jun So Pak, Heeseok Lee, Minkyu Mike Kim, Ilryong Kim
{"title":"Analysis on Optimal Chip Floorplanning Considering Various Types of Decoupling Capacitors in Package PDN","authors":"Jisoo Hwang, James Jeong, Heejung Choi, Jun So Pak, Heeseok Lee, Minkyu Mike Kim, Ilryong Kim","doi":"10.1109/ectc51906.2022.00329","DOIUrl":null,"url":null,"abstract":"In this paper, to improve PI (Power Integrity) performance of system-level PDN (Power Delivery Network), the optimal arrangement of various package decoupling capacitors and on-chip IPs (Intellectual Property) are analyzed from the co-design point of view. By applying decoupling capacitor to the package PDN, impedance peak of the system-level PDN can be lowered in the frequency domain, and so does the voltage drop in the time domain. In this paper, the PI performance improvement effect according to the location of the package decoupling capacitor is analyzed. Furthermore, it is confirmed that the inductance generated in the package PDN should be reduced to optimize the PI improvement effect of the package decoupling capacitor. A method to reduce the inductance of such package PDN, especially bump-to-decap inductance, is analyzed from the co-design point of view of on-chip PDN and package PDN. Therefore, in this paper, it is proposed what should be considered in the chip floorplanning stage for optimization of PDN from IP to DSC, especially for the case where DSC is applied.","PeriodicalId":139520,"journal":{"name":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ectc51906.2022.00329","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

In this paper, to improve PI (Power Integrity) performance of system-level PDN (Power Delivery Network), the optimal arrangement of various package decoupling capacitors and on-chip IPs (Intellectual Property) are analyzed from the co-design point of view. By applying decoupling capacitor to the package PDN, impedance peak of the system-level PDN can be lowered in the frequency domain, and so does the voltage drop in the time domain. In this paper, the PI performance improvement effect according to the location of the package decoupling capacitor is analyzed. Furthermore, it is confirmed that the inductance generated in the package PDN should be reduced to optimize the PI improvement effect of the package decoupling capacitor. A method to reduce the inductance of such package PDN, especially bump-to-decap inductance, is analyzed from the co-design point of view of on-chip PDN and package PDN. Therefore, in this paper, it is proposed what should be considered in the chip floorplanning stage for optimization of PDN from IP to DSC, especially for the case where DSC is applied.
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封装PDN中考虑不同类型去耦电容的最优芯片布局分析
为了提高系统级PDN (Power Delivery Network)的功率完整性(PI)性能,从协同设计的角度分析了各种封装去耦电容器和片上知识产权(ip)的最佳配置。通过在封装PDN上施加去耦电容,可以在频域降低系统级PDN的阻抗峰值,在时域降低电压降。本文分析了封装去耦电容位置对PI性能的改善效果。进一步验证了应减小封装PDN中产生的电感,以优化封装去耦电容的PI改善效果。从片上PDN和封装PDN协同设计的角度,分析了减小封装PDN电感,特别是碰撞到封盖电感的方法。因此,本文提出了PDN从IP到DSC的优化,特别是在应用DSC的情况下,在芯片布局阶段应该考虑的问题。
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