{"title":"Power analysis of a 32-bit embedded microcontroller","authors":"V. Tiwari, M. Lee","doi":"10.1109/ASPDAC.1995.486215","DOIUrl":null,"url":null,"abstract":"A new approach for power analysis of microprocessors has recently been proposed (Tiwari et al 1994). The idea is to look at the power consumption in a microprocessor from the point of view of the actual software executing on the processor. The basic component of this approach is a measurement based, instruction-level power analysis technique. The technique allows for the development of an instruction-level power model for the given processor, which can be used to evaluate software in terms of the power consumption, and for exploring the optimization of software for lower power. This paper describes the application of this technique for a comprehensive instruction-level power analysis of a commercial 32-bit RISC-based embedded microcontroller. The salient results of the analysis and the basic instruction-level power model are described. Interesting observations and insights based on the results are also presented. Such an instruction-level power analysis can provide cues as to what optimizations in the micro-architecture design of the processor would lead to the most effective power savings in actual software applications. Wherever the results indicate such optimizations, they have been discussed. Furthermore, ideas for low power software design, as suggested by the results, are described in this paper as well.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"82 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"99","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.1995.486215","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 99
Abstract
A new approach for power analysis of microprocessors has recently been proposed (Tiwari et al 1994). The idea is to look at the power consumption in a microprocessor from the point of view of the actual software executing on the processor. The basic component of this approach is a measurement based, instruction-level power analysis technique. The technique allows for the development of an instruction-level power model for the given processor, which can be used to evaluate software in terms of the power consumption, and for exploring the optimization of software for lower power. This paper describes the application of this technique for a comprehensive instruction-level power analysis of a commercial 32-bit RISC-based embedded microcontroller. The salient results of the analysis and the basic instruction-level power model are described. Interesting observations and insights based on the results are also presented. Such an instruction-level power analysis can provide cues as to what optimizations in the micro-architecture design of the processor would lead to the most effective power savings in actual software applications. Wherever the results indicate such optimizations, they have been discussed. Furthermore, ideas for low power software design, as suggested by the results, are described in this paper as well.
最近提出了一种新的微处理器功耗分析方法(Tiwari et al . 1994)。这个想法是从处理器上执行的实际软件的角度来看微处理器的功耗。该方法的基本组成部分是基于测量的指导性功率分析技术。该技术允许为给定处理器开发指令级功耗模型,该模型可用于根据功耗评估软件,并用于探索低功耗软件的优化。本文介绍了该技术在商用32位risc嵌入式微控制器的综合指令级功耗分析中的应用。介绍了分析的显著结果和基本指令级功率模型。还介绍了基于结果的有趣观察和见解。这种指令级功耗分析可以提供线索,说明处理器微架构设计中的哪些优化将导致实际软件应用程序中最有效的功耗节省。只要结果表明了这种优化,就会对其进行讨论。此外,根据研究结果提出了低功耗软件设计的思路,并在本文中进行了描述。