Automatic insertion of gated clocks at register transfer level

Abstract

In synchronous circuits, the clock signal switches at every clock cycle and drives a large capacitance. As a result, the clock signal is a major source of dynamic power dissipation. Significant power savings can be obtained by identifying periods of inactivity in parts of the circuit, and disabling the clock to those parts of the circuit at the appropriate times. Selectively disabling the clock in this manner is referred to as clock gating. In this paper/sup 1/, we present a methodology to identify registers and flip flops in a circuit for which the clock input can be gated with a control signal. We also generate the combinational logic to produce this control signal. We present an algorithm to estimate the power saving obtained by gating the clock and the performance penalty (if any) associated with the introduction of gating logic. The algorithm generates the clock gating logic which is inserted appropriately into the original circuit to produce a low power, gated clock version of the circuit.