{"title":"Passive model-order reduction of RLC circuits with embedded time-delay descriptor systems","authors":"A. Charest, M. Nakhla, R. Achar","doi":"10.1109/EPEPS.2011.6100232","DOIUrl":null,"url":null,"abstract":"In this paper, a new algorithm for passive model-order reduction of RLC networks with embedded general Time-Delay Descriptor (TDD) systems is presented. In addition, a new passivity verification algorithm for TDD systems is developed. Numerical results validating the proposed algorithms are also presented.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEPS.2011.6100232","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In this paper, a new algorithm for passive model-order reduction of RLC networks with embedded general Time-Delay Descriptor (TDD) systems is presented. In addition, a new passivity verification algorithm for TDD systems is developed. Numerical results validating the proposed algorithms are also presented.
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