Overview of the prospects of ultra-rapid thermal process for advanced CMOSFETs

Abstract

This paper presents ultra shallow junction with low resistance in 45-65nm technology node. Rapid thermal annealing is required to form ultra-shallow, low sheet resistance and lower dislocation density for satisfying the pn junction leakage specification of mobile LSIs. In order to minimize the annealing time at high temperatures, various kinds of ultra-rapid thermal annealing technology such as advanced spike RTA, laser annealing, SPE, flash lamp annealing are compared. Issues of this technology are simultaneously accomplishing ultrashallow Xj, lower sheet resistance and lower crystal damage density for fabricating advanced MOSFETs. By optimizing various process conditions, we can successfully obtain ultra shallow p+/n and n+/p junction of less than 10 nm. In this paper, we overview the prospects for ultra-rapid thermal process for advanced CMOSFETs.