{"title":"A Design of 5.8GHz Tunable Band Noise Cancelling CMOS LNA for DSRC Communications","authors":"Dong Won Lee, Kangyoon Lee","doi":"10.1109/ISOCC50952.2020.9332934","DOIUrl":null,"url":null,"abstract":"This article presents about 5.8GHz noise cancelling CMOS LNA for DSRC communication. The LNA is designed with differential output with balun architecture and resistive-feedback noise cancelling technique. Tunable load capacitor bank achieves wideband input matching and gain selection. The LNA is implemented in 130nm CMOS technology and achieves a simulated gain of 24.2dB and PldB of -13.46dB and noise figure(NF) of 2.74dB at center frequency. The power consumption is 10.51mW at 1.2V power supply. The chip area is 509×559µm2","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC50952.2020.9332934","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This article presents about 5.8GHz noise cancelling CMOS LNA for DSRC communication. The LNA is designed with differential output with balun architecture and resistive-feedback noise cancelling technique. Tunable load capacitor bank achieves wideband input matching and gain selection. The LNA is implemented in 130nm CMOS technology and achieves a simulated gain of 24.2dB and PldB of -13.46dB and noise figure(NF) of 2.74dB at center frequency. The power consumption is 10.51mW at 1.2V power supply. The chip area is 509×559µm2
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
