System aware DUT design for optimum on-wafer noise measurement

Abstract

This paper presents a system-aware design of device-under-tests (DUT) for optimum high-frequency (HF) on-wafer noise measurement. It overcomes the challenges in modeling the bias and geometry dependence of noise sources due to the voltage drop in the interconnections at the output port of a large DUT. It also prevents the measurement inaccuracy resulted from insufficient noise from a small DUT. Experimental data and suggested device sizes for different technologies are presented.