A back-to-face silicon layer stacking for three-dimensional integration

Abstract

We have successfully demonstrated a back-to-face ultra-thin silicon layer stacking based on low temperature wafer bonding and etch-back. This type of silicon layer stacking can be expanded to wafers with device and interconnect layers to fabricate three-dimensional integrated circuits (3D ICs). Electrical connection between layers can be achieved by interlayer vertical via formed by bonded Cu layers.