Technology mapping for sequential circuits based on retiming techniques

Abstract

A new technology mapping technique for implementing sequential circuits by table lookup FPGAs (field programmable gate arrays) with predefined memory elements is presented. Most mapping algorithms in this field are restricted to combinational logic. The presented methods for optimizing delay and area consumption are based on a redesign of the circuit with retiming and specific sequential transformations. Experimental results of several benchmark circuits show an improvement of up to 20% less area consumption and delay in comparison to existing tools.<>