Cell area minimization by transistor folding

Abstract

Tall transistors can be folded into shorter ones to reduce the layout area. The authors take two rows of transistors, one for P-type transistors and the other for N-type transistors, and attempt to determine an optimal folding for each transistor to minimize the layout area. They present an O(K/sup 3/L/sup 3/) time transistor folding algorithm to minimize the layout area, where K is the number of implementations of each transistor due to folding, and L is the channel length.<>