On using a SPICE-like TSTAC™ eFlash model for design and test

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2011-04-13 DOI:10.1109/DDECS.2011.5783111

Pierre-Didier Mauroux, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, B. Godard, G. Festes, L. Vachez

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引用次数: 1

Abstract

The Flash technology is the most popular non-volatile memory technology. In this paper, we present the ability of a SPICE-like model of the ATMEL TSTAC™ eFlash technology to guide the design and test phases. This model is composed of two layers: a functional layer representing the Floating Gate (FG) and a programming layer able to determine the channel voltage level controlling the Fowler-Nordheim tunneling effect. It is able to guide the test phase since it allows analyzing and modeling defects that may affect the eFlash array. This analysis highlights the interest of the proposed model to identify a realistic set of fault models that has to be tested, thus enhancing existing solutions for TSTAC™ eFlash testing. The proposed model is also helpful to guide the design phase. Data presented in the paper demonstrate its accuracy compared to silicon measurements, usefulness to predict the technology shrinking and usefulness to guide the pulse programming method.

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关于使用SPICE-like TSTAC™eFlash模型进行设计和测试

Flash技术是最流行的非易失性存储技术。在本文中，我们介绍了ATMEL TSTAC™eFlash技术的SPICE-like模型来指导设计和测试阶段的能力。该模型由两层组成:代表浮栅(FG)的功能层和能够确定控制Fowler-Nordheim隧穿效应的通道电压水平的编程层。它能够指导测试阶段，因为它允许分析和建模可能影响eFlash阵列的缺陷。这一分析突出了所提出的模型对确定一组必须进行测试的实际故障模型的兴趣，从而增强了TSTAC™eFlash测试的现有解决方案。所提出的模型也有助于指导设计阶段。本文给出的数据表明，该方法与硅测量方法相比具有精度，对预测工艺收缩和指导脉冲编程方法具有实用价值。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

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