{"title":"Pipelined, time-sharing access technique for a highly integrated multi-port memory","authors":"T. Matsumura, K. Endo, J. Yamada","doi":"10.1109/VLSIC.1990.111118","DOIUrl":null,"url":null,"abstract":"A pipelined, time-sharing access (PTA) technique that enables a two-port memory cell to operate as a four-port memory cell is proposed. The effectiveness of this technique has been demonstrated by fabricating a 64-kb four-port (read/write) memory with 60-MHz operation under a 3-V supply voltage","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1990.111118","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A pipelined, time-sharing access (PTA) technique that enables a two-port memory cell to operate as a four-port memory cell is proposed. The effectiveness of this technique has been demonstrated by fabricating a 64-kb four-port (read/write) memory with 60-MHz operation under a 3-V supply voltage
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