A Low Phase Noise Fractional-N PLL for mmWave Telecom and RADAR Applications

Abstract

This paper presents a fractional N Phase Locked Loop (PLL) integrated circuit (IC) implemented in 65nm bulk CMOS, targeting mmWave and RADAR applications. The IC is comprised of a PLL with integrated active loop filter and Voltage-Controlled Oscillator (VCO) and auxiliary blocks such as auto-calibration unit, ramp generator, bandgap reference, lock detector and bias circuits. The PLL uses an external reference frequency 40-320MHz and provides a local oscillator (LO) output signal in the range [8.8–9.9]GHz with low phase noise (PN) and output power 0dBm on a 50 Ohm load. The total silicon area is $2.2\times 0.76 \text{mm}^{2}$ and its power consumption is 270mW from a 1.8V supply.