A high speed reconfigurable gate array for gigahertz applications

Abstract

This paper describes the implementation of the next generation of a scalable SiGe FPGA in the latest IBM 8HP SiGe process (fT = 210GHz) that serves as an interleaving and de-interleaving block in a high speed reconfigurable data acquisition system. In this paper, different generations of SiGe configurable blocks (basic cells) are presented and measured. The latest generation has a 94% reduction in power consumption (from 71mW to 4.2mW) and an 83% reduction of the propagation delay (from 238ps to 42ps) compared to the first generation design. To demonstrate the SiGe FPGA's capabilities of handling GHz signals, the SiGe FPGAs are configured as a multiplexer (MUX), de-multiplexer (DEMUX) and pseudo-SERDES. For the IBM 8HP process, the MUX, DEMUX and pseudo-SERDES can achieve a transmission rate of 28Gbps. For the previous IBM 7HP case, the 4:1 multiplexer runs at a transmission rate of 8Gbps. With these design results, the SiGe FPGA is able to process GHz signals such as S and K microwave bands.