A sub-pW timer using gate leakage for ultra low-power sub-Hz monitoring systems

Abstract

In this work, we present a novel ultra-low power timer designed using the gate leakage of MOS capacitors. The test chip was fabricated in a 0.13 mum CMOS technology and the total circuit area is 480 mum2. Measurement results show that the circuit functions correctly at a wide range of supply voltages from 300 mV to 1.2 V, making it particularly suitable for subthreshold systems. The temperature sensitivity is 0.16%/degC at 600 mV and 0.6%/degC at 300 mV. The power dissipation is less than 1pW running at 20degC and 300 mV.