In-depth soft error vulnerability analysis using synthetic benchmarks

Abstract

Statistical fault injection is widely used for analyzing hardware in the presence of soft errors. Although this method can give accurate results for averaged erroneous outcomes with a fairly small sample size, it will not be accurate for vulnerability analysis of each sequential element in the design with small sample sizes. This paper describes a novel and highly efficient technique which is suitable for detailed vulnerability analysis of a processor. The technique involves specific sets of assembly language routines, and is shown to be much more efficient and comprehensive compared with traditional statistical error injection on a predetermined set of benchmarks. We have shown the effectiveness of the method using error injection in an ARM Amber25 processor model. Our analysis is based on more than 330,000 simulation runs with single bit-flips on the sequential elements of this processor running our synthetic benchmarks and 40,000 FPGA-based error injections for 4 conventional benchmarks.