Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116303
Ben Niewenhuis, R. D. Blanton
Fast and efficient analysis of test chips is crucial for effective yield learning. Prior work proposed the Carnegie-Mellon logic characterization vehicle (CM-LCV) as an improved test chip for yield learning. The highly regular nature of the CM-LCV test chip is particularly appealing for BIST; the current work describes a BIST scheme that achieves 100% input-pattern fault coverage with an 86.9% reduction in test time for a reference design. Furthermore, all of these properties are achieved with a minimal hardware overhead.
{"title":"Efficient built-in self test of regular logic characterization vehicles","authors":"Ben Niewenhuis, R. D. Blanton","doi":"10.1109/VTS.2015.7116303","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116303","url":null,"abstract":"Fast and efficient analysis of test chips is crucial for effective yield learning. Prior work proposed the Carnegie-Mellon logic characterization vehicle (CM-LCV) as an improved test chip for yield learning. The highly regular nature of the CM-LCV test chip is particularly appealing for BIST; the current work describes a BIST scheme that achieves 100% input-pattern fault coverage with an 86.9% reduction in test time for a reference design. Furthermore, all of these properties are achieved with a minimal hardware overhead.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127225312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116286
K. Gent, M. Hsiao
Functional test generation and design validation frequently use stochastic methods for vector generation. However, for circuits with narrow paths or random-resistant corner cases, purely random techniques can fail to produce adequate results. Deterministic techniques can aid this process; however, they add significant computational complexity. This paper presents a Register Transfer Level (RTL) abstraction technique to derive relationships between inputs and path activations. The abstractions are built off of various program slices. Using such a variety of abstracted RTL models, we attempt to find patterns in the reduced state and input with their resulting branch activations. These relationships are then applied to guide stimuli generation in the concrete model. Experimental results show that this method allows for fast convergence on hard-to-reach states and achieves a performance increase of up to 9× together with a reduction of test lengths compared to previous hybrid search techniques.
{"title":"Abstraction-based relation mining for functional test generation","authors":"K. Gent, M. Hsiao","doi":"10.1109/VTS.2015.7116286","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116286","url":null,"abstract":"Functional test generation and design validation frequently use stochastic methods for vector generation. However, for circuits with narrow paths or random-resistant corner cases, purely random techniques can fail to produce adequate results. Deterministic techniques can aid this process; however, they add significant computational complexity. This paper presents a Register Transfer Level (RTL) abstraction technique to derive relationships between inputs and path activations. The abstractions are built off of various program slices. Using such a variety of abstracted RTL models, we attempt to find patterns in the reduced state and input with their resulting branch activations. These relationships are then applied to guide stimuli generation in the concrete model. Experimental results show that this method allows for fast convergence on hard-to-reach states and achieves a performance increase of up to 9× together with a reduction of test lengths compared to previous hybrid search techniques.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129273639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116260
Harry H. Chen, Shih-Hua Kuo, Jonathan Tung, M. Chao
In this paper we describe a novel scheme for collecting and analyzing a chip's failure signature. Incorrect outputs of digital chips are forced by applying scan patterns under non-destructive stress conditions. From binary mismatch responses collected in continue-on-fail mode, numeric data features are formed by grouping and counting mismatches in each group, thus defining a chip's “analog” failure signature. We use machine learning to explore prediction models of system-level test (SLT) failures by comparing signatures of chip samples from known SLT pass/fail bins. Important features that clearly separate the SLT pass/fail chips are identified. Experimental results are presented for a 28-nm 1.2-GHz quad-core low-power processor.
{"title":"Statistical techniques for predicting system-level failure using stress-test data","authors":"Harry H. Chen, Shih-Hua Kuo, Jonathan Tung, M. Chao","doi":"10.1109/VTS.2015.7116260","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116260","url":null,"abstract":"In this paper we describe a novel scheme for collecting and analyzing a chip's failure signature. Incorrect outputs of digital chips are forced by applying scan patterns under non-destructive stress conditions. From binary mismatch responses collected in continue-on-fail mode, numeric data features are formed by grouping and counting mismatches in each group, thus defining a chip's “analog” failure signature. We use machine learning to explore prediction models of system-level test (SLT) failures by comparing signatures of chip samples from known SLT pass/fail bins. Important features that clearly separate the SLT pass/fail chips are identified. Experimental results are presented for a 28-nm 1.2-GHz quad-core low-power processor.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130548595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116278
R. Fei, Jocelyn Moreau, S. Mir, Alexis Marcellin, C. Mandier, E. Huss, G. Palmigiani, P. Vitrou, Thomas Droniou
Current production testing of CMOS imager sensors is mainly based on capturing images and detecting failures by image processing with special algorithms. The fault coverage of this costly optical test is not sufficient given the quality requirements. Studies on devices produced at large volume have shown that Horizontal Fixed Pattern Noise (HFPN) is one of the common image failures encountered on products that present fault coverage problems, and this is the main cause of customer returns for many products. A detailed analysis of failed devices has demonstrated that HFPN failures arise from changes of electronic circuit topology in pixel addressing decoders or the metal lines required for pixel powering and control. These changes are usually due to the presence of spot defects, causing some pixels in a row to operate incorrectly, leading to an HFPN failure. Moreover, defects resulting in partially degraded metal lines may not induce image failure in limited industrial test conditions, passing the optical tests. Later, these defects may produce an image failure in the field, either because the capture conditions would be more stringent, or because the defects would evolve into catastrophic faults due to electromigration. In this paper, we have first enhanced the HFPN detection algorithm in order to improve the fault coverage of the optical test. Next, a built-in self-test structure is presented for the on-chip detection of catastrophic and non-catastrophic defects in the pixel power and control lines.
{"title":"Horizontal-FPN fault coverage improvement in production test of CMOS imagers","authors":"R. Fei, Jocelyn Moreau, S. Mir, Alexis Marcellin, C. Mandier, E. Huss, G. Palmigiani, P. Vitrou, Thomas Droniou","doi":"10.1109/VTS.2015.7116278","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116278","url":null,"abstract":"Current production testing of CMOS imager sensors is mainly based on capturing images and detecting failures by image processing with special algorithms. The fault coverage of this costly optical test is not sufficient given the quality requirements. Studies on devices produced at large volume have shown that Horizontal Fixed Pattern Noise (HFPN) is one of the common image failures encountered on products that present fault coverage problems, and this is the main cause of customer returns for many products. A detailed analysis of failed devices has demonstrated that HFPN failures arise from changes of electronic circuit topology in pixel addressing decoders or the metal lines required for pixel powering and control. These changes are usually due to the presence of spot defects, causing some pixels in a row to operate incorrectly, leading to an HFPN failure. Moreover, defects resulting in partially degraded metal lines may not induce image failure in limited industrial test conditions, passing the optical tests. Later, these defects may produce an image failure in the field, either because the capture conditions would be more stringent, or because the defects would evolve into catastrophic faults due to electromigration. In this paper, we have first enhanced the HFPN detection algorithm in order to improve the fault coverage of the optical test. Next, a built-in self-test structure is presented for the on-chip detection of catastrophic and non-catastrophic defects in the pixel power and control lines.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121521352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116257
Doohwang Chang, B. Bakkaloglu, S. Ozev
With increasing diversity of supply chains from design to delivery, there is an increasing risk of unauthorized changes within an IC. One of the motivations for this type change is to learn important information (such as encryption keys, spreading codes) from the hardware and pass this information to a malicious party through wireless means. In order to evade detection, such unauthorized communication can be hidden within legitimate bursts of transmit signal. In this paper, we present a stealth circuit for unauthorized transmissions which can be hidden within the legitimate signal. A CDMA-based spread spectrum with a CDMA encoder is implemented with a handful of transistors. We show that the unauthorized signal does not alter the circuit performance while being easily detectable by the malicious receiver.
{"title":"Enabling unauthorized RF transmission below noise floor with no detectable impact on primary communication performance","authors":"Doohwang Chang, B. Bakkaloglu, S. Ozev","doi":"10.1109/VTS.2015.7116257","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116257","url":null,"abstract":"With increasing diversity of supply chains from design to delivery, there is an increasing risk of unauthorized changes within an IC. One of the motivations for this type change is to learn important information (such as encryption keys, spreading codes) from the hardware and pass this information to a malicious party through wireless means. In order to evade detection, such unauthorized communication can be hidden within legitimate bursts of transmit signal. In this paper, we present a stealth circuit for unauthorized transmissions which can be hidden within the legitimate signal. A CDMA-based spread spectrum with a CDMA encoder is implemented with a handful of transistors. We show that the unauthorized signal does not alter the circuit performance while being easily detectable by the malicious receiver.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114694051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116276
Gurgen Harutunyan, Grigor Tshagharyan, Y. Zorian
The technology shrinking strategy below 20nm feature sizes adopted by the giants of the nowadays semiconductor industry has boosted the research on FinFET which is considered as an alternative to the conventional planar technology. This paper presents a comprehensive study carried out for FinFET-based memories using an advanced flow for fault modeling and test algorithm generation. Using this flow it has been shown that parameter variation (of process, voltage, temperature, frequency) has a significant impact on the fault coverage when dealing with FinFET-specific faults.
{"title":"Impact of parameter variations on FinFET faults","authors":"Gurgen Harutunyan, Grigor Tshagharyan, Y. Zorian","doi":"10.1109/VTS.2015.7116276","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116276","url":null,"abstract":"The technology shrinking strategy below 20nm feature sizes adopted by the giants of the nowadays semiconductor industry has boosted the research on FinFET which is considered as an alternative to the conventional planar technology. This paper presents a comprehensive study carried out for FinFET-based memories using an advanced flow for fault modeling and test algorithm generation. Using this flow it has been shown that parameter variation (of process, voltage, temperature, frequency) has a significant impact on the fault coverage when dealing with FinFET-specific faults.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115087345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116248
Li Xu, Yan Duan, Degang Chen
Clock jitter is a crucial factor in high speed and high performance application. Traditional jitter measurement method relies on precise and expensive instrumentations. This paper proposes a low cost jitter measurement and separation method. Instead of using traditional time internal analysis equipment, a simple Analog-to-Digital Converter (ADC) is used as the jitter measurement device. The clock under test is applied as the sampling clock of an ADC while the ADC is sampling a full scale sine wave. The ADC output contains the information of the clock jitter. The algorithm will separately detect the effects of Periodic Jitter, Dual-Dirac Jitter and Random Jitter, and accurately compute the rms value of each jitter component. This method offers great potential for wide use in low cost applications and especially in on-chip or on-board jitter measurement applications. Simulation results demonstrate the functionality, accuracy and robustness of the proposed low-cost jitter measurement method.
{"title":"A low cost jitter separation and characterization method","authors":"Li Xu, Yan Duan, Degang Chen","doi":"10.1109/VTS.2015.7116248","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116248","url":null,"abstract":"Clock jitter is a crucial factor in high speed and high performance application. Traditional jitter measurement method relies on precise and expensive instrumentations. This paper proposes a low cost jitter measurement and separation method. Instead of using traditional time internal analysis equipment, a simple Analog-to-Digital Converter (ADC) is used as the jitter measurement device. The clock under test is applied as the sampling clock of an ADC while the ADC is sampling a full scale sine wave. The ADC output contains the information of the clock jitter. The algorithm will separately detect the effects of Periodic Jitter, Dual-Dirac Jitter and Random Jitter, and accurately compute the rms value of each jitter component. This method offers great potential for wide use in low cost applications and especially in on-chip or on-board jitter measurement applications. Simulation results demonstrate the functionality, accuracy and robustness of the proposed low-cost jitter measurement method.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128688475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116297
I. Pomeranz
Test vector omission is a static test compaction procedure for functional test sequences that removes unnecessary test vectors from a sequence. The test vector omission procedure requires fault simulation for every test vector (or subsequence) that it considers for omission. It was noted earlier that it is possible to reduce the set of simulated faults based on the clock cycles where the faults are detected. However, this reduction is effective only for the later test vectors of a sequence. This paper defines a minimal set of faults that need to be simulated for the omission of a test vector by considering, in addition to detection clock cycles, also clock cycles where test subsequences start. The former are computed by a conventional sequential fault simulation process. For the latter, the paper introduces a sequential reverse order fault simulation process, and an approximation with a reduced computational complexity. Experimental results show significant reductions in the run time for test vector omission without affecting the level of compaction.
{"title":"Test vector omission with minimal sets of simulated faults","authors":"I. Pomeranz","doi":"10.1109/VTS.2015.7116297","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116297","url":null,"abstract":"Test vector omission is a static test compaction procedure for functional test sequences that removes unnecessary test vectors from a sequence. The test vector omission procedure requires fault simulation for every test vector (or subsequence) that it considers for omission. It was noted earlier that it is possible to reduce the set of simulated faults based on the clock cycles where the faults are detected. However, this reduction is effective only for the later test vectors of a sequence. This paper defines a minimal set of faults that need to be simulated for the omission of a test vector by considering, in addition to detection clock cycles, also clock cycles where test subsequences start. The former are computed by a conventional sequential fault simulation process. For the latter, the paper introduces a sequential reverse order fault simulation process, and an approximation with a reduced computational complexity. Experimental results show significant reductions in the run time for test vector omission without affecting the level of compaction.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130726132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116245
Kai Hu, B. Bhattacharya, K. Chakrabarty
Advances in flow-based microfluidics allow biochemistry-on-a-chip for DNA sequencing, drug discovery, and point-of-care disease diagnosis. However, the adoption of flow-based biochips is hampered by defects that frequently occur in chips fabricated using soft lithography techniques. Fault diagnosis methods are now needed to improve fabrication processes and facilitate the (partial) use of chips that have defects. We present the first approach for the automated diagnosis of flow-based microfluidic biochips. The proposed method facilitates the identification of defects through syndrome analysis and a hitting-set problem formulation. The proposed technique is evaluated using three fabricated biochips, and exact defect localization and identification of the defect type is achieved in all cases.
{"title":"Fault diagnosis for flow-based microfluidic biochips","authors":"Kai Hu, B. Bhattacharya, K. Chakrabarty","doi":"10.1109/VTS.2015.7116245","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116245","url":null,"abstract":"Advances in flow-based microfluidics allow biochemistry-on-a-chip for DNA sequencing, drug discovery, and point-of-care disease diagnosis. However, the adoption of flow-based biochips is hampered by defects that frequently occur in chips fabricated using soft lithography techniques. Fault diagnosis methods are now needed to improve fabrication processes and facilitate the (partial) use of chips that have defects. We present the first approach for the automated diagnosis of flow-based microfluidic biochips. The proposed method facilitates the identification of defects through syndrome analysis and a hitting-set problem formulation. The proposed technique is evaluated using three fabricated biochips, and exact defect localization and identification of the defect type is achieved in all cases.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132391013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116298
I. Pomeranz
Test compaction that accommodates the constraints of test data compression can be achieved by generating test cubes for target faults, and then merging the test cubes. This paper describes an improved test cube merging procedure for four-way bridging faults. The procedure is motivated by the prevalence of bridging defects and the fact that test sets for bridging faults are larger than test sets for single stuck-at faults. A four-way bridging fault gi/ai/hi models the case where a value ai of a line hi dominates the value of a line gi. A basic test cube merging procedure considers a set of test cubes Cdet that detects target faults. The paper extends the set of test cubes to include, in addition to Cdet, a set of test cubes Cdom that assign values to dominating lines. Test cubes from Cdom have significantly fewer specified values than test cubes from Cdet. When test cubes from Cdom are merged with test cubes from Cdet, each resulting test cube detects more faults, and fewer test cubes are needed for detecting the same set of target faults.
{"title":"Test compaction by test cube merging for four-way bridging faults","authors":"I. Pomeranz","doi":"10.1109/VTS.2015.7116298","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116298","url":null,"abstract":"Test compaction that accommodates the constraints of test data compression can be achieved by generating test cubes for target faults, and then merging the test cubes. This paper describes an improved test cube merging procedure for four-way bridging faults. The procedure is motivated by the prevalence of bridging defects and the fact that test sets for bridging faults are larger than test sets for single stuck-at faults. A four-way bridging fault g<sub>i</sub>/a<sub>i</sub>/h<sub>i</sub> models the case where a value a<sub>i</sub> of a line h<sub>i</sub> dominates the value of a line g<sub>i</sub>. A basic test cube merging procedure considers a set of test cubes C<sub>det</sub> that detects target faults. The paper extends the set of test cubes to include, in addition to C<sub>det</sub>, a set of test cubes C<sub>dom</sub> that assign values to dominating lines. Test cubes from C<sub>dom</sub> have significantly fewer specified values than test cubes from C<sub>det</sub>. When test cubes from C<sub>dom</sub> are merged with test cubes from C<sub>det</sub>, each resulting test cube detects more faults, and fewer test cubes are needed for detecting the same set of target faults.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125381064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：