A. Marchlewski, H. Zimmermann, I. Jonak-Auer, E. Wachmann
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引用次数: 0
Abstract
In this work we present the usability of the translinear loop topology as frontend sensing circuit for broadband OEIC chip design in a 0.35µm SiGe BiCMOS technology. The result is a fully monolithically integrated 1-Gbps optical receiver with a sensitivity of −20dBm at 675nm in a mature silicon-based technology, which is appropriate e. g. as a plastic optical fiber (POF) receiver or generally as receiver in short-range optical interconnects.
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