{"title":"A wideband CMOS VCO for zero-IF GSM-CDMA single-chip transceiver","authors":"Kostas Manetakis, D. Jessie, C. Narathong","doi":"10.1109/ESSCIR.2004.1356637","DOIUrl":null,"url":null,"abstract":"This paper presents a low-power CMOS VCO in a 0.35 /spl mu/m process which achieves a tuning range of 2.47 GHz-3.47 GHz and phase noise performance of -145dBc/Hz at 3 MHz offset (from a 1.8 GHz carrier). 5-bit digital coarse-tuning and accumulation-type MOS varactors allow for a 33% tuning range, which is required to cover the LO frequency range of a zero-IF GSM-CDMA transceiver and to account for process and temperature variations. Optimum design techniques ensure low VCO gain (<104 MHz/V) for good interoperability with the frequency synthesizer. An integrated regulator provides low supply pushing (40 kHz/V) and reduces the AM-to-PM sensitivity from the supply.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"147 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 30th European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIR.2004.1356637","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper presents a low-power CMOS VCO in a 0.35 /spl mu/m process which achieves a tuning range of 2.47 GHz-3.47 GHz and phase noise performance of -145dBc/Hz at 3 MHz offset (from a 1.8 GHz carrier). 5-bit digital coarse-tuning and accumulation-type MOS varactors allow for a 33% tuning range, which is required to cover the LO frequency range of a zero-IF GSM-CDMA transceiver and to account for process and temperature variations. Optimum design techniques ensure low VCO gain (<104 MHz/V) for good interoperability with the frequency synthesizer. An integrated regulator provides low supply pushing (40 kHz/V) and reduces the AM-to-PM sensitivity from the supply.